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Line 98... |
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CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
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CSR_MSCRATCH = 0x340, /**< 0x340 - mscratch (r/w): Machine scratch register */
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CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
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CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
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CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
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CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/w): Machine trap cause */
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CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
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CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/w): Machine bad address or instruction */
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CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
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CSR_MIP = 0x344, /**< 0x344 - mip (r/-): Machine interrupt pending register */
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CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
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CSR_PMPCFG0 = 0x3a0, /**< 0x3a0 - pmpcfg0 (r/w): Physical memory protection configuration register 0 */
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CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
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CSR_PMPCFG1 = 0x3a1, /**< 0x3a1 - pmpcfg1 (r/w): Physical memory protection configuration register 1 */
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CSR_PMPCFG2 = 0x3a2, /**< 0x3a2 - pmpcfg2 (r/w): Physical memory protection configuration register 2 */
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CSR_PMPCFG2 = 0x3a2, /**< 0x3a2 - pmpcfg2 (r/w): Physical memory protection configuration register 2 */
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CSR_PMPCFG3 = 0x3a3, /**< 0x3a3 - pmpcfg3 (r/w): Physical memory protection configuration register 3 */
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CSR_PMPCFG3 = 0x3a3, /**< 0x3a3 - pmpcfg3 (r/w): Physical memory protection configuration register 3 */
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Line 509... |
CSR_MZEXT_ZBB = 2, /**< CPU mzext CSR (2): Zbb extension (B sub-extension) available when set (r/-) */
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CSR_MZEXT_ZBB = 2, /**< CPU mzext CSR (2): Zbb extension (B sub-extension) available when set (r/-) */
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CSR_MZEXT_ZBS = 3, /**< CPU mzext CSR (3): Zbs extension (B sub-extension) available when set (r/-) */
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CSR_MZEXT_ZBS = 3, /**< CPU mzext CSR (3): Zbs extension (B sub-extension) available when set (r/-) */
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CSR_MZEXT_ZBA = 4, /**< CPU mzext CSR (4): Zba extension (B sub-extension) available when set (r/-) */
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CSR_MZEXT_ZBA = 4, /**< CPU mzext CSR (4): Zba extension (B sub-extension) available when set (r/-) */
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CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
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CSR_MZEXT_ZFINX = 5, /**< CPU mzext CSR (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
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CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
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CSR_MZEXT_ZXSCNT = 6, /**< CPU mzext CSR (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
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CSR_MZEXT_ZXNOCNT = 7 /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
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CSR_MZEXT_ZXNOCNT = 7, /**< CPU mzext CSR (7): Custom extension - NO CPU counters: "cycle" & "instret" CSRs are NOT available at all when set (r/-) */
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CSR_MZEXT_PMP = 8, /**< CPU mzext CSR (8): PMP (physical memory protection) extension available when set (r/-) */
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CSR_MZEXT_HPM = 9 /**< CPU mzext CSR (9): HPM (hardware performance monitors) extension available when set (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mhpmevent</b> hardware performance monitor events
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* CPU <b>mhpmevent</b> hardware performance monitor events
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Line 553... |
TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */
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TRAP_CODE_L_ACCESS = 0x00000005, /**< 0.5: Load (bus) access fault */
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TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
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TRAP_CODE_S_MISALIGNED = 0x00000006, /**< 0.6: Store address misaligned */
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TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */
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TRAP_CODE_S_ACCESS = 0x00000007, /**< 0.7: Store (bus) access fault */
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TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */
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TRAP_CODE_UENV_CALL = 0x00000008, /**< 0.8: Environment call from user mode (ECALL instruction) */
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TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
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TRAP_CODE_MENV_CALL = 0x0000000b, /**< 0.11: Environment call from machine mode (ECALL instruction) */
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TRAP_CODE_NMI = 0x80000000, /**< 1.0: Non-maskable interrupt */
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TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */
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TRAP_CODE_MSI = 0x80000003, /**< 1.3: Machine software interrupt */
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TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */
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TRAP_CODE_MTI = 0x80000007, /**< 1.7: Machine timer interrupt */
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TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */
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TRAP_CODE_MEI = 0x8000000b, /**< 1.11: Machine external interrupt */
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TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
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TRAP_CODE_FIRQ_0 = 0x80000010, /**< 1.16: Fast interrupt channel 0 */
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TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
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TRAP_CODE_FIRQ_1 = 0x80000011, /**< 1.17: Fast interrupt channel 1 */
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