| Line 432... |
Line 432... |
HPMCNT_EVENT_ILLEGAL = 14 /**< CPU mhpmevent CSR (14): Illegal instruction exception */
|
HPMCNT_EVENT_ILLEGAL = 14 /**< CPU mhpmevent CSR (14): Illegal instruction exception */
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};
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};
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|
|
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/**********************************************************************//**
|
/**********************************************************************//**
|
|
* CPU <b>pmpcfg</b> PMP configuration attributed
|
|
**************************************************************************/
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enum NEORV32_PMPCFG_ATTRIBUTES_enum {
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|
PMPCFG_R = 0, /**< CPU pmpcfg attribute (0): Read */
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PMPCFG_W = 1, /**< CPU pmpcfg attribute (1): Write */
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PMPCFG_X = 2, /**< CPU pmpcfg attribute (2): Execute */
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PMPCFG_A_LSB = 3, /**< CPU pmpcfg attribute (3): Mode LSB */
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PMPCFG_A_MSB = 4, /**< CPU pmpcfg attribute (4): Mode MSB */
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PMPCFG_L = 7 /**< CPU pmpcfg attribute (7): Locked */
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|
};
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|
|
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/**********************************************************************//**
|
|
* PMP modes
|
|
**************************************************************************/
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#define PMPCFG_MODE_NAPOT 3
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|
|
|
|
|
/**********************************************************************//**
|
* Trap codes from mcause CSR.
|
* Trap codes from mcause CSR.
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_EXCEPTION_CODES_enum {
|
enum NEORV32_EXCEPTION_CODES_enum {
|
TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
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TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
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TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
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TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
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| Line 731... |
Line 749... |
SLINK_CTRL_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */
|
SLINK_CTRL_TX_FIFO_S0 = 12, /**< SLINK control register(12) (r/-): log2(TX FIFO size) bit 0 */
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SLINK_CTRL_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */
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SLINK_CTRL_TX_FIFO_S1 = 13, /**< SLINK control register(13) (r/-): log2(TX FIFO size) bit 1 */
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SLINK_CTRL_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */
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SLINK_CTRL_TX_FIFO_S2 = 14, /**< SLINK control register(14) (r/-): log2(TX FIFO size) bit 2 */
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SLINK_CTRL_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */
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SLINK_CTRL_TX_FIFO_S3 = 15, /**< SLINK control register(15) (r/-): log2(TX FIFO size) bit 3 */
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|
|
SLINK_CTRL_EN = 31, /**< SLINK control register(0) (r/w): SLINK controller enable */
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SLINK_CTRL_EN = 31 /**< SLINK control register(0) (r/w): SLINK controller enable */
|
};
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};
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|
|
/** SLINK interrupt control register bits */
|
/** SLINK interrupt control register bits */
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enum NEORV32_SLINK_IRQ_enum {
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enum NEORV32_SLINK_IRQ_enum {
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SLINK_IRQ_RX_EN_LSB = 0, /**< SLINK IRQ configuration register( 0) (r/w): RX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */
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SLINK_IRQ_RX_EN_LSB = 0, /**< SLINK IRQ configuration register( 0) (r/w): RX IRQ enable LSB (link 0) (#NEORV32_SLINK_IRQ_EN_enum) */
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| Line 755... |
Line 773... |
SLINK_IRQ_ENABLE = 1 /**< '0': IRQ enabled */
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SLINK_IRQ_ENABLE = 1 /**< '0': IRQ enabled */
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};
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};
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/** SLINK RX interrupt configuration type (per link) */
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/** SLINK RX interrupt configuration type (per link) */
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enum NEORV32_SLINK_IRQ_RX_TYPE_enum {
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enum NEORV32_SLINK_IRQ_RX_TYPE_enum {
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SLINK_IRQ_RX_FIFO_HALF = 0, /**< '0': RX FIFO fill-level rises above half-full */
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SLINK_IRQ_RX_NOT_EMPTY = 0, /**< '1': RX FIFO is not empty */
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SLINK_IRQ_RX_NOT_EMPTY = 1 /**< '1': RX FIFO is not empty */
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SLINK_IRQ_RX_FIFO_HALF = 1 /**< '0': RX FIFO fill-level rises above half-full */
|
};
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};
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|
|
/** SLINK TX interrupt configuration type (per link) */
|
/** SLINK TX interrupt configuration type (per link) */
|
enum NEORV32_SLINK_IRQ_TX_TYPE_enum {
|
enum NEORV32_SLINK_IRQ_TX_TYPE_enum {
|
SLINK_IRQ_TX_FIFO_HALF = 0, /**< '0': TX FIFO fill-level falls below half-full */
|
SLINK_IRQ_TX_NOT_FULL = 0, /**< '1': TX FIFO is not FULL */
|
SLINK_IRQ_TX_NOT_FULL = 1 /**< '1': TX FIFO is not FULL */
|
SLINK_IRQ_TX_FIFO_HALF = 1 /**< '0': TX FIFO fill-level falls below half-full */
|
};
|
};
|
|
|
/** SLINK status register bits */
|
/** SLINK status register bits */
|
enum NEORV32_SLINK_STATUS_enum {
|
enum NEORV32_SLINK_STATUS_enum {
|
SLINK_STATUS_RX0_AVAIL = 0, /**< SLINK status register(0) (r/-): RX link 0 FIFO is NOT empty (data available) */
|
SLINK_STATUS_RX0_AVAIL = 0, /**< SLINK status register(0) (r/-): RX link 0 FIFO is NOT empty (data available) */
|
| Line 827... |
Line 845... |
enum NEORV32_GPTMR_CTRL_enum {
|
enum NEORV32_GPTMR_CTRL_enum {
|
GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
|
GPTMR_CTRL_EN = 0, /**< GPTIMR control register(0) (r/w): Timer unit enable */
|
GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
|
GPTMR_CTRL_PRSC0 = 1, /**< GPTIMR control register(1) (r/w): Clock prescaler select bit 0 */
|
GPTMR_CTRL_PRSC1 = 2, /**< GPTIMR control register(2) (r/w): Clock prescaler select bit 1 */
|
GPTMR_CTRL_PRSC1 = 2, /**< GPTIMR control register(2) (r/w): Clock prescaler select bit 1 */
|
GPTMR_CTRL_PRSC2 = 3, /**< GPTIMR control register(3) (r/w): Clock prescaler select bit 2 */
|
GPTMR_CTRL_PRSC2 = 3, /**< GPTIMR control register(3) (r/w): Clock prescaler select bit 2 */
|
GPTMR_CTRL_MODE = 4, /**< GPTIMR control register(4) (r/w): Timer mode: 0=single-shot mode, 1=continuous mode */
|
GPTMR_CTRL_MODE = 4 /**< GPTIMR control register(4) (r/w): Timer mode: 0=single-shot mode, 1=continuous mode */
|
GPTMR_CTRL_ALARM = 5 /**< GPTIMR control register(5) (r/c): Interrupt/alarm pending, cleared by setting bit to zero */
|
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 1090... |
Line 1107... |
WDT_CTRL_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */
|
WDT_CTRL_CLK_SEL2 = 3, /**< WDT control register(3) (r/w): Clock prescaler select bit 2 */
|
WDT_CTRL_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */
|
WDT_CTRL_MODE = 4, /**< WDT control register(4) (r/w): Watchdog mode: 0=timeout causes interrupt, 1=timeout causes processor reset */
|
WDT_CTRL_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
|
WDT_CTRL_RCAUSE = 5, /**< WDT control register(5) (r/-): Cause of last system reset: 0=external reset, 1=watchdog */
|
WDT_CTRL_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */
|
WDT_CTRL_RESET = 6, /**< WDT control register(6) (-/w): Reset WDT counter when set, auto-clears */
|
WDT_CTRL_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */
|
WDT_CTRL_FORCE = 7, /**< WDT control register(7) (-/w): Force WDT action, auto-clears */
|
WDT_CTRL_LOCK = 8 /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */
|
WDT_CTRL_LOCK = 8, /**< WDT control register(8) (r/w): Lock write access to control register, clears on reset (HW or WDT) only */
|
|
WDT_CTRL_DBEN = 9, /**< WDT control register(9) (r/w): Allow WDT to continue operation even when in debug mode */
|
|
WDT_CTRL_HALF = 10 /**< WDT control register(10) (r/-): Set if at least half of the max. timeout counter value has been reached */
|
};
|
};
|
/**@}*/
|
/**@}*/
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 1193... |
Line 1212... |
SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
|
SYSINFO_CPU_ZIFENCEI = 1, /**< SYSINFO_CPU (1): Zifencei extension (I sub-extension) available when set (r/-) */
|
SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
|
SYSINFO_CPU_ZMMUL = 2, /**< SYSINFO_CPU (2): Zmmul extension (M sub-extension) available when set (r/-) */
|
|
|
SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
|
SYSINFO_CPU_ZFINX = 5, /**< SYSINFO_CPU (5): Zfinx extension (F sub-/alternative-extension) available when set (r/-) */
|
SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
|
SYSINFO_CPU_ZXSCNT = 6, /**< SYSINFO_CPU (6): Custom extension - Small CPU counters: "cycle" & "instret" CSRs have less than 64-bit when set (r/-) */
|
SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basie CPU counters available when set (r/-) */
|
SYSINFO_CPU_ZICNTR = 7, /**< SYSINFO_CPU (7): Basic CPU counters available when set (r/-) */
|
SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
|
SYSINFO_CPU_PMP = 8, /**< SYSINFO_CPU (8): PMP (physical memory protection) extension available when set (r/-) */
|
SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
|
SYSINFO_CPU_ZIHPM = 9, /**< SYSINFO_CPU (9): HPM (hardware performance monitors) extension available when set (r/-) */
|
SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
|
SYSINFO_CPU_DEBUGMODE = 10, /**< SYSINFO_CPU (10): RISC-V CPU debug mode available when set (r/-) */
|
|
|
SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
|
SYSINFO_CPU_FASTMUL = 30, /**< SYSINFO_CPU (30): fast multiplications (via FAST_MUL_EN generic) available when set (r/-) */
|
| Line 1211... |
Line 1230... |
SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
|
SYSINFO_SOC_MEM_INT_IMEM = 2, /**< SYSINFO_FEATURES (2) (r/-): Processor-internal instruction memory implemented when 1 (via MEM_INT_IMEM_EN generic) */
|
SYSINFO_SOC_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
|
SYSINFO_SOC_MEM_INT_DMEM = 3, /**< SYSINFO_FEATURES (3) (r/-): Processor-internal data memory implemented when 1 (via MEM_INT_DMEM_EN generic) */
|
SYSINFO_SOC_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
|
SYSINFO_SOC_MEM_EXT_ENDIAN = 4, /**< SYSINFO_FEATURES (4) (r/-): External bus interface uses BIG-endian byte-order when 1 (via MEM_EXT_BIG_ENDIAN generic) */
|
SYSINFO_SOC_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
|
SYSINFO_SOC_ICACHE = 5, /**< SYSINFO_FEATURES (5) (r/-): Processor-internal instruction cache implemented when 1 (via ICACHE_EN generic) */
|
|
|
|
SYSINFO_SOC_IS_SIM = 13, /**< SYSINFO_FEATURES (13) (r/-): Set during simulation (not guaranteed) */
|
SYSINFO_SOC_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
|
SYSINFO_SOC_OCD = 14, /**< SYSINFO_FEATURES (14) (r/-): On-chip debugger implemented when 1 (via ON_CHIP_DEBUGGER_EN generic) */
|
SYSINFO_SOC_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
|
SYSINFO_SOC_HW_RESET = 15, /**< SYSINFO_FEATURES (15) (r/-): Dedicated hardware reset of core registers implemented when 1 (via package's dedicated_reset_c constant) */
|
|
|
SYSINFO_SOC_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
|
SYSINFO_SOC_IO_GPIO = 16, /**< SYSINFO_FEATURES (16) (r/-): General purpose input/output port unit implemented when 1 (via IO_GPIO_EN generic) */
|
SYSINFO_SOC_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
|
SYSINFO_SOC_IO_MTIME = 17, /**< SYSINFO_FEATURES (17) (r/-): Machine system timer implemented when 1 (via IO_MTIME_EN generic) */
|
| Line 1258... |
Line 1278... |
|
|
|
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
// Include all IO driver headers
|
// Include all IO driver headers
|
// ----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------
|
// legacy compatibility layer
|
|
#include "neorv32_legacy.h"
|
|
|
|
// cpu core
|
// cpu core
|
#include "neorv32_cpu.h"
|
#include "neorv32_cpu.h"
|
|
|
// intrinsics
|
// intrinsics
|
#include "neorv32_intrinsics.h"
|
#include "neorv32_intrinsics.h"
|
