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Line 67... |
**************************************************************************/
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**************************************************************************/
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extern int __neorv32_crt0_after_main(int32_t return_code) __attribute__ ((weak));
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extern int __neorv32_crt0_after_main(int32_t return_code) __attribute__ ((weak));
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/**********************************************************************//**
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/**********************************************************************//**
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* Store unsigned word to address space.
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* Store unsigned word to address space if atomic access reservation is still valid.
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*
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*
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* @note An unaligned access address will raise an alignment exception.
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* @note An unaligned access address will raise an alignment exception.
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*
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*
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* @param[in] addr Address (32-bit).
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data word (32-bit) to store.
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* @param[in] wdata Data word (32-bit) to store.
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* @return Operation status (32-bit).
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* @return Operation status (32-bit, zero if success).
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**************************************************************************/
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**************************************************************************/
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_store_conditional(uint32_t addr, uint32_t wdata) {
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inline uint32_t __attribute__ ((always_inline)) neorv32_cpu_store_conditional(uint32_t addr, uint32_t wdata) {
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#if defined __riscv_atomic || defined __riscv_a
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#if defined __riscv_atomic || defined __riscv_a
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register uint32_t reg_addr = addr;
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register uint32_t reg_addr = addr;
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Line 92... |
#endif
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#endif
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Conditional store unsigned word to address space if atomic access reservation is valid.
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* Conditional store unsigned word to address space.
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*
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*
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* @note An unaligned access address will raise an alignment exception.
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* @note An unaligned access address will raise an alignment exception.
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*
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*
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* @param[in] addr Address (32-bit).
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* @param[in] addr Address (32-bit).
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* @param[in] wdata Data word (32-bit) to store.
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* @param[in] wdata Data word (32-bit) to store.
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Line 252... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Put CPU into "sleep" mode.
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* Put CPU into "sleep" mode.
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*
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*
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* @note This function executes the WFI insstruction.
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* @note This function executes the WFI instruction.
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* The WFI (wait for interrupt) instruction will make the CPU stall until
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* The WFI (wait for interrupt) instruction will make the CPU stall until
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* an interupt request is detected. Interrupts have to be globally enabled
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* an interrupt request is detected. Interrupts have to be globally enabled
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* and at least one external source must be enabled (like the MTI machine
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* and at least one external source must be enabled (like the MTI machine
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* timer interrupt) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
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* timer interrupt) to allow the CPU to wake up again. If 'Zicsr' CPU extension is disabled,
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* this will permanently stall the CPU.
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* this will permanently stall the CPU.
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**************************************************************************/
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**************************************************************************/
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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inline void __attribute__ ((always_inline)) neorv32_cpu_sleep(void) {
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