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#include "neorv32.h"
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#include "neorv32.h"
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#include "neorv32_cpu.h"
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#include "neorv32_cpu.h"
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable/disable CPU extension during runtime via the 'misa' CSR.
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*
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* @warning This is still highly experimental! This function requires the Zicsr + Zifencei CPU extensions.
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*
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* @param[in] sel Bit to be set in misa CSR / extension to be enabled. See #NEORV32_CPU_MISA_enum.
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* @param[in] state Set 1 to enable the selected extension, set 0 to disable it;
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* return 0 if success, 1 if error (invalid sel or extension cannot be enabled).
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**************************************************************************/
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int neorv32_cpu_switch_extension(int sel, int state) {
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// get current misa setting
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uint32_t misa_curr = neorv32_cpu_csr_read(CSR_MISA);
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uint32_t misa_prev = misa_curr;
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// abort if misa.z is cleared
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if ((misa_curr & (1 << CPU_MISA_Z_EXT)) == 0) {
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return 1;
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}
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// out of range?
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if (sel > 25) {
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return 1;
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}
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// enable/disable selected extension
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if (state & 1) {
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misa_curr |= (1 << sel);
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}
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else {
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misa_curr &= ~(1 << sel);
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}
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// try updating misa
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neorv32_cpu_csr_write(CSR_MISA, misa_curr);
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asm volatile("fence.i"); // required to flush prefetch buffers
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asm volatile("nop");
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// dit it work?
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if (neorv32_cpu_csr_read(CSR_MISA) == misa_prev) {
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return 1; // nope
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}
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else {
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return 0; // fine
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}
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}
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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* Enable specific CPU interrupt.
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*
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CPU_MIE_enum.
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