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Line 45... |
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/**********************************************************************//**
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/**********************************************************************//**
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* >Private< helper functions.
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* >Private< helper functions.
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**************************************************************************/
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**************************************************************************/
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static int __neorv32_cpu_irq_id_check(uint8_t irq_sel);
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static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
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static uint32_t __neorv32_cpu_pmp_cfg_read(uint32_t index);
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static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
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static void __neorv32_cpu_pmp_cfg_write(uint32_t index, uint32_t data);
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/**********************************************************************//**
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/**********************************************************************//**
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* Private function: Check IRQ id.
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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static int __neorv32_cpu_irq_id_check(uint8_t irq_sel) {
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if ((irq_sel == CSR_MIE_MSIE) || (irq_sel == CSR_MIE_MTIE) || (irq_sel == CSR_MIE_MEIE) ||
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(irq_sel == CSR_MIE_FIRQ0E) || (irq_sel == CSR_MIE_FIRQ1E) || (irq_sel == CSR_MIE_FIRQ2E) || (irq_sel == CSR_MIE_FIRQ3E) ||
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(irq_sel == CSR_MIE_FIRQ4E) || (irq_sel == CSR_MIE_FIRQ5E) || (irq_sel == CSR_MIE_FIRQ6E) || (irq_sel == CSR_MIE_FIRQ7E)) {
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return 0;
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}
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else {
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return 1;
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}
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}
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/**********************************************************************//**
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* Enable specific CPU interrupt.
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* Enable specific CPU interrupt.
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*
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*
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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* @note Interrupts have to be globally enabled via neorv32_cpu_eint(void), too.
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*
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*
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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int neorv32_cpu_irq_enable(uint8_t irq_sel) {
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if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) &&
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// check IRQ id
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(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) {
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if (__neorv32_cpu_irq_id_check(irq_sel)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrs zero, mie, %0" : : "r" (mask));
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Line 98... |
* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @param[in] irq_sel CPU interrupt select. See #NEORV32_CSR_MIE_enum.
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* @return 0 if success, 1 if error (invalid irq_sel).
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* @return 0 if success, 1 if error (invalid irq_sel).
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**************************************************************************/
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**************************************************************************/
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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int neorv32_cpu_irq_disable(uint8_t irq_sel) {
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if ((irq_sel != CSR_MIE_MSIE) && (irq_sel != CSR_MIE_MTIE) && (irq_sel != CSR_MIE_MEIE) &&
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// check IRQ id
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(irq_sel != CSR_MIE_FIRQ0E) && (irq_sel != CSR_MIE_FIRQ1E) && (irq_sel != CSR_MIE_FIRQ2E) && (irq_sel != CSR_MIE_FIRQ3E)) {
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if (__neorv32_cpu_irq_id_check(irq_sel)) {
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return 1;
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return 1;
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}
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}
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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register uint32_t mask = (uint32_t)(1 << irq_sel);
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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asm volatile ("csrrc zero, mie, %0" : : "r" (mask));
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