| Line 329... |
Line 329... |
*
|
*
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* @return Returns number of available PMP regions.
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* @return Returns number of available PMP regions.
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**************************************************************************/
|
**************************************************************************/
|
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
|
uint32_t neorv32_cpu_pmp_get_num_regions(void) {
|
|
|
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// PMP implemented at all?
|
|
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_PMP)) == 0) {
|
|
return 0;
|
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}
|
|
|
uint32_t i = 0;
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uint32_t i = 0;
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|
|
// try setting R bit in all PMPCFG CSRs
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// try setting R bit in all PMPCFG CSRs
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const uint32_t tmp = 0x01010101;
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const uint32_t tmp = 0x01010101;
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for (i=0; i<16; i++) {
|
for (i=0; i<16; i++) {
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| Line 585... |
Line 590... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* Hardware performance monitors (HPM): Get number of available HPM counters.
|
* Hardware performance monitors (HPM): Get number of available HPM counters.
|
*
|
*
|
* @warning This function overrides all available mhpmcounter* CSRs.
|
* @warning This function overrides all available mhpmcounter* CSRs.
|
*
|
*
|
* @return Returns number of available HPM counters (..29).
|
* @return Returns number of available HPM counters (0..29).
|
**************************************************************************/
|
**************************************************************************/
|
uint32_t neorv32_cpu_hpm_get_counters(void) {
|
uint32_t neorv32_cpu_hpm_get_counters(void) {
|
|
|
|
// HPMs implemented at all?
|
|
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_HPM)) == 0) {
|
|
return 0;
|
|
}
|
|
|
// inhibit all HPM counters
|
// inhibit all HPM counters
|
uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
|
uint32_t tmp = neorv32_cpu_csr_read(CSR_MCOUNTINHIBIT);
|
tmp |= 0xfffffff8;
|
tmp |= 0xfffffff8;
|
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp);
|
neorv32_cpu_csr_write(CSR_MCOUNTINHIBIT, tmp);
|
|
|
| Line 663... |
Line 673... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* Hardware performance monitors (HPM): Get total counter width
|
* Hardware performance monitors (HPM): Get total counter width
|
*
|
*
|
* @warning This function overrides mhpmcounter3[h] CSRs.
|
* @warning This function overrides mhpmcounter3[h] CSRs.
|
*
|
*
|
* @return Size of HPM counter bits (1-64).
|
* @return Size of HPM counter bits (1-64, 0 if not implemented at all).
|
**************************************************************************/
|
**************************************************************************/
|
uint32_t neorv32_cpu_hpm_get_size(void) {
|
uint32_t neorv32_cpu_hpm_get_size(void) {
|
|
|
|
// HPMs implemented at all?
|
|
if ((neorv32_cpu_csr_read(CSR_MZEXT) & (1<<CSR_MZEXT_HPM)) == 0) {
|
|
return 0;
|
|
}
|
|
|
// inhibt auto-update
|
// inhibt auto-update
|
asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTEREN_HPM3));
|
asm volatile ("csrwi %[addr], %[imm]" : : [addr] "i" (CSR_MCOUNTINHIBIT), [imm] "i" (1<<CSR_MCOUNTEREN_HPM3));
|
|
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0xffffffff);
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3, 0xffffffff);
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3H, 0xffffffff);
|
neorv32_cpu_csr_write(CSR_MHPMCOUNTER3H, 0xffffffff);
|
