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Line 88... |
PWM_CT &= ~((uint32_t)(1 << PWM_CT_EN));
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PWM_CT &= ~((uint32_t)(1 << PWM_CT_EN));
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Set duty cycle for channel. The PWM duty cycle bits are listed in #NEORV32_PWM_DUTY_enum.
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* Get number of implemented channels.
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* @warning This function will override all duty cycle configuration registers.
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*
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*
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* @param[in] channel Channel select (0..3).
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* @return Number of implemented channels.
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**************************************************************************/
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int neorv32_pmw_get_num_channels(void) {
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neorv32_pwm_disable();
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uint8_t index = 0;
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uint8_t cnt = 0;
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for (index=0; index<60; index++) {
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neorv32_pwm_set(index, 1);
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cnt += neorv32_pwm_get(index);
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}
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return (int)cnt;
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}
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/**********************************************************************//**
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* Set duty cycle for channel.
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*
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* @param[in] channel Channel select (0..59).
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* @param[in] duty Duty cycle (0..255).
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* @param[in] duty Duty cycle (0..255).
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**************************************************************************/
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**************************************************************************/
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void neorv32_pwm_set(uint8_t channel, uint8_t duty) {
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void neorv32_pwm_set(uint8_t channel, uint8_t duty) {
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channel = channel & 0x03;
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if (channel > 59) {
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return; // out-of-range
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}
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// compute duty-cycle offset
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uint32_t reg_offset = (uint32_t)(channel / 4);
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uint8_t byte_offset = channel % 4;
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// read-modify-write
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uint32_t duty_mask = 0xff;
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uint32_t duty_mask = 0xff;
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uint32_t duty_new = (uint32_t)duty;
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uint32_t duty_new = (uint32_t)duty;
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duty_mask = duty_mask << (channel * 8);
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duty_mask = duty_mask << (byte_offset * 8);
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duty_new = duty_new << (channel * 8);
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duty_new = duty_new << (byte_offset * 8);
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uint32_t duty_cycle = PWM_DUTY;
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uint32_t duty_cycle = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
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duty_cycle &= ~duty_mask; // clear previous duty cycle
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duty_cycle &= ~duty_mask; // clear previous duty cycle
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duty_cycle |= duty_new; // set new duty cycle
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duty_cycle |= duty_new; // set new duty cycle
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PWM_DUTY = duty_cycle;
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(*(IO_REG32 (&PWM_DUTY0 + reg_offset))) = duty_cycle;
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}
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/**********************************************************************//**
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* Get duty cycle from channel.
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*
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* @param[in] channel Channel select (0..59).
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* @return Duty cycle (0..255) of channel 'channel'.
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**************************************************************************/
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uint8_t neorv32_pwm_get(uint8_t channel) {
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if (channel > 59) {
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return 0; // out-of-range
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}
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// compute duty-cycle offset
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uint32_t reg_offset = (uint32_t)(channel / 4);
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uint8_t byte_offset = channel % 4;
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// read
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uint32_t tmp = (*(IO_REG32 (&PWM_DUTY0 + reg_offset)));
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tmp = tmp >> ((byte_offset * 8));
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return (uint8_t)tmp;
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}
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}
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No newline at end of file
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No newline at end of file
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