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Line 44... |
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// Privates
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// Privates
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static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_dummy_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_debug_exc_handler(void) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_hw_version(void) __attribute__((unused));
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/**********************************************************************//**
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/**********************************************************************//**
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* Setup NEORV32 runtime environment in debug mode.
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* Setup NEORV32 runtime environment in debug mode.
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*
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*
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| Line 92... |
Line 91... |
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if (exc_id == EXCID_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt
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if (exc_id == EXCID_MSI) { neorv32_cpu_irq_enable(CPU_MIE_MSIE); } // activate software interrupt
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if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
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if (exc_id == EXCID_MTI) { neorv32_cpu_irq_enable(CPU_MIE_MTIE); } // activate timer interrupt
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if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
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if (exc_id == EXCID_MEI) { neorv32_cpu_irq_enable(CPU_MIE_MEIE); } // activate external interrupt
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uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
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uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
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vt_base = vt_base + (((uint32_t)exc_id) << 2);
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vt_base = vt_base + (((uint32_t)exc_id) << 2);
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(*(IO_REG32 (vt_base))) = (uint32_t)handler;
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(*(IO_REG32 (vt_base))) = (uint32_t)handler;
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return 0;
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return 0;
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}
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}
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if (exc_id == EXCID_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt
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if (exc_id == EXCID_MSI) { neorv32_cpu_irq_disable(CPU_MIE_MSIE); } // deactivate software interrupt
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if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
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if (exc_id == EXCID_MTI) { neorv32_cpu_irq_disable(CPU_MIE_MTIE); } // deactivate timer interrupt
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if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
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if (exc_id == EXCID_MEI) { neorv32_cpu_irq_disable(CPU_MIE_MEIE); } // deactivate external interrupt
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uint32_t vt_base = neorv32_cpu_csr_read(CSR_MDSPACEBASE); // base address of vector table
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uint32_t vt_base = SYSINFO_DSPACE_BASE; // base address of vector table
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vt_base = vt_base + (((uint32_t)exc_id) << 2);
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vt_base = vt_base + (((uint32_t)exc_id) << 2);
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(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered
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(*(IO_REG32 (vt_base))) = (uint32_t)(&__neorv32_rte_dummy_exc_handler); // use dummy handler in case the exception is triggered
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return 0;
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return 0;
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}
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}
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Line 158... |
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_inst;
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register uint32_t trap_inst;
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// get faulting instruction
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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if (trap_cause & 0x80000000) {
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if (trap_cause & 0x80000000) {
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neorv32_uart_printf("INTERRUPT");
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neorv32_uart_printf("INTERRUPT");
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}
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}
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else {
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else {
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neorv32_uart_printf("EXCEPTION");
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neorv32_uart_printf("EXCEPTION");
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case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;
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case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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}
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}
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// fault address
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// fault address
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neorv32_uart_printf("\nFaulting instruction: 0x%x\n", trap_inst);
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neorv32_uart_printf("\nFaulting instruction (low): 0x%x\n", trap_inst);
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neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
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neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
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if ((trap_inst & 3) != 3) {
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if ((trap_inst & 3) != 3) {
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neorv32_uart_printf("(decompressed)\n");
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neorv32_uart_printf("(decompressed)\n");
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}
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}
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// CPU configuration
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// CPU configuration
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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neorv32_uart_printf("\n-- Central Processing Unit --\n");
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// Hart ID
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// Hart ID
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neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
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neorv32_uart_printf("Hart ID: %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
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// Custom user code
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neorv32_uart_printf("User code: 0x%x\n", SYSINFO_USER_CODE);
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// HW version
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// HW version
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neorv32_uart_printf("Hardware version: ");
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neorv32_uart_printf("Hardware version: ");
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__neorv32_rte_print_hw_version();
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neorv32_rte_print_hw_version();
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neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
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neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
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// CPU architecture
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// CPU architecture
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neorv32_uart_printf("Architecture: ");
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neorv32_uart_printf("Architecture: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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Line 260... |
neorv32_uart_putc(' ');
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neorv32_uart_putc(' ');
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}
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}
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}
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}
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neorv32_uart_printf("(0x%x)\n", tmp);
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neorv32_uart_printf("(0x%x)\n", tmp);
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// Performance counters
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neorv32_uart_printf("CNT & time CSRs: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_CSR_COUNTERS));
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// Clock speed
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// Clock speed
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neorv32_uart_printf("Clock speed: %u Hz\n", neorv32_cpu_csr_read(CSR_MCLOCK));
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neorv32_uart_printf("Clock speed: %u Hz\n", SYSINFO_CLK);
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// Memory configuration
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// Memory configuration
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neorv32_uart_printf("\n-- Memory Configuration --\n");
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neorv32_uart_printf("\n-- Memory Configuration --\n");
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uint32_t size = neorv32_cpu_csr_read(CSR_MISPACESIZE);
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uint32_t size = SYSINFO_ISPACE_SIZE;
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uint32_t base = neorv32_cpu_csr_read(CSR_MISPACEBASE);
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uint32_t base = SYSINFO_ISPACE_BASE;
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neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Internal IMEM: ");
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neorv32_uart_printf("Internal IMEM: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
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neorv32_uart_printf("Internal IMEM as ROM: ");
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neorv32_uart_printf("Internal IMEM as ROM: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_IMEM_ROM));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
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size = neorv32_cpu_csr_read(CSR_MDSPACESIZE);
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size = SYSINFO_DSPACE_SIZE;
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base = neorv32_cpu_csr_read(CSR_MDSPACEBASE);
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base = SYSINFO_DSPACE_BASE;
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neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Data memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Internal DMEM: ");
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neorv32_uart_printf("Internal DMEM: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_INT_DMEM));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
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neorv32_uart_printf("Bootloader: ");
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neorv32_uart_printf("Bootloader: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_BOOTLOADER));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
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neorv32_uart_printf("External interface: ");
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neorv32_uart_printf("External interface: ");
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__neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MFEATURES) & (1 << CPU_MFEATURES_MEM_EXT));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
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// peripherals
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// peripherals
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neorv32_uart_printf("\n-- Peripherals --\n");
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neorv32_uart_printf("\n-- Peripherals --\n");
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tmp = neorv32_cpu_csr_read(CSR_MFEATURES);
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tmp = SYSINFO_FEATURES;
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neorv32_uart_printf("GPIO: ");
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neorv32_uart_printf("GPIO: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_GPIO));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
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neorv32_uart_printf("MTIME: ");
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neorv32_uart_printf("MTIME: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_MTIME));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
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neorv32_uart_printf("UART: ");
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neorv32_uart_printf("UART: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_UART));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART));
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neorv32_uart_printf("SPI: ");
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neorv32_uart_printf("SPI: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_SPI));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
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neorv32_uart_printf("TWI: ");
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neorv32_uart_printf("TWI: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TWI));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
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neorv32_uart_printf("PWM: ");
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neorv32_uart_printf("PWM: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_PWM));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
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neorv32_uart_printf("WDT: ");
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neorv32_uart_printf("WDT: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_WDT));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
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neorv32_uart_printf("CLIC: ");
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neorv32_uart_printf("CLIC: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_CLIC));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CLIC));
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neorv32_uart_printf("TRNG: ");
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neorv32_uart_printf("TRNG: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_TRNG));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
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neorv32_uart_printf("DEVNULL: ");
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neorv32_uart_printf("DEVNULL: ");
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__neorv32_rte_print_true_false(tmp & (1 << CPU_MFEATURES_IO_DEVNULL));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* NEORV32 runtime environment: Private function to print true or false.
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* NEORV32 runtime environment: Private function to print true or false.
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| Line 342... |
Line 340... |
}
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}
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* NEORV32 runtime environment: Private function to show the processor version in human-readable format.
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* NEORV32 runtime environment: Function to show the processor version in human-readable format.
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* @note This function is used by neorv32_rte_print_hw_config(void) only.
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**************************************************************************/
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**************************************************************************/
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static void __neorv32_rte_print_hw_version(void) {
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void neorv32_rte_print_hw_version(void) {
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uint32_t i;
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uint32_t i;
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char tmp, cnt;
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char tmp, cnt;
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uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
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uint32_t version = neorv32_cpu_csr_read(CSR_MIMPID);
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