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* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
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* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
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* @note This function is used by neorv32_rte_exception_uninstall(void) only.
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* @note This function is used by neorv32_rte_exception_uninstall(void) only.
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**************************************************************************/
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**************************************************************************/
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static void __neorv32_rte_debug_exc_handler(void) {
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static void __neorv32_rte_debug_exc_handler(void) {
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neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");
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// intro
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neorv32_uart_printf("<RTE> ");
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neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));
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// cause
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_inst;
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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if (trap_cause & 0x80000000) {
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neorv32_uart_printf("INTERRUPT");
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}
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else {
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neorv32_uart_printf("EXCEPTION");
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if ((trap_inst & 3) == 3) {
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trap_addr -= 4;
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}
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else {
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trap_addr -= 2;
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}
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}
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neorv32_uart_printf(" at instruction address: 0x%x\n", trap_addr);
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neorv32_uart_printf("Cause: ");
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switch (trap_cause) {
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switch (trap_cause) {
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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}
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}
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// fault address
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// address
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neorv32_uart_printf("\nFaulting instruction (low half word): 0x%x", trap_inst);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_inst;
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if ((trap_inst & 3) != 3) {
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neorv32_uart_printf(" (decompressed)\n");
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}
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neorv32_uart_printf("\nMTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
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neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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neorv32_uart_printf("\n<</NEORV32 Runtime Environment >>\n\n");
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if ((trap_cause & 0x80000000) == 0) {
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if ((trap_inst & 3) == 3) {
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trap_addr -= 4;
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}
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else {
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trap_addr -= 2;
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}
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}
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neorv32_uart_printf(" @0x%x, MTVAL=0x%x </RTE>", trap_addr, neorv32_cpu_csr_read(CSR_MTVAL));
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* NEORV32 runtime environment: Print hardware configuration information via UART
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* NEORV32 runtime environment: Print hardware configuration information via UART
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neorv32_uart_putc(' ');
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neorv32_uart_putc(' ');
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}
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}
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}
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}
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neorv32_uart_printf("(0x%x)\n", tmp);
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neorv32_uart_printf("(0x%x)\n", tmp);
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// Clock speed
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neorv32_uart_printf("Clock speed: %u Hz\n", SYSINFO_CLK);
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// Misc
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neorv32_uart_printf("\n-- System --\n");
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neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
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// Memory configuration
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// Memory configuration
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neorv32_uart_printf("\n-- Memory Configuration --\n");
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neorv32_uart_printf("\n-- Processor Memory Configuration --\n");
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uint32_t size = SYSINFO_ISPACE_SIZE;
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uint32_t size = SYSINFO_ISPACE_SIZE;
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uint32_t base = SYSINFO_ISPACE_BASE;
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uint32_t base = SYSINFO_ISPACE_BASE;
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neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Instruction memory: %u bytes @ 0x%x\n", size, base);
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neorv32_uart_printf("Internal IMEM: ");
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neorv32_uart_printf("Internal IMEM: ");
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neorv32_uart_printf("External interface: ");
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neorv32_uart_printf("External interface: ");
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
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__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
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// peripherals
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// peripherals
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neorv32_uart_printf("\n-- Peripherals --\n");
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neorv32_uart_printf("\n-- Processor Peripherals --\n");
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tmp = SYSINFO_FEATURES;
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tmp = SYSINFO_FEATURES;
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neorv32_uart_printf("GPIO: ");
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neorv32_uart_printf("GPIO: ");
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
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__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
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