| Line 80... |
Line 80... |
* @note Interrupt sources have to be explicitly enabled by the user via the CSR.mie bits via neorv32_cpu_irq_enable(uint8_t irq_sel)
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* @note Interrupt sources have to be explicitly enabled by the user via the CSR.mie bits via neorv32_cpu_irq_enable(uint8_t irq_sel)
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* and the global interrupt enable bit mstatus.mie via neorv32_cpu_eint(void).
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* and the global interrupt enable bit mstatus.mie via neorv32_cpu_eint(void).
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*
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*
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
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* @param[in] handler The actual handler function for the specified exception (function MUST be of type "void function(void);").
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* return 0 if success, 1 if error (invalid id or targeted exception not supported).
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* @return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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**************************************************************************/
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int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
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int neorv32_rte_exception_install(uint8_t id, void (*handler)(void)) {
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|
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// id valid?
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// id valid?
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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| Line 107... |
Line 107... |
*
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*
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* @note Interrupt sources have to be explicitly disabled by the user via the CSR.mie bits via neorv32_cpu_irq_disable(uint8_t irq_sel)
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* @note Interrupt sources have to be explicitly disabled by the user via the CSR.mie bits via neorv32_cpu_irq_disable(uint8_t irq_sel)
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* and/or the global interrupt enable bit mstatus.mie via neorv32_cpu_dint(void).
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* and/or the global interrupt enable bit mstatus.mie via neorv32_cpu_dint(void).
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*
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*
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* @param[in] id Identifier (type) of the targeted exception. See #NEORV32_RTE_TRAP_enum.
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* return 0 if success, 1 if error (invalid id or targeted exception not supported).
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* @return 0 if success, 1 if error (invalid id or targeted exception not supported).
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**************************************************************************/
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**************************************************************************/
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int neorv32_rte_exception_uninstall(uint8_t id) {
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int neorv32_rte_exception_uninstall(uint8_t id) {
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|
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// id valid?
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// id valid?
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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if ((id == RTE_TRAP_I_MISALIGNED) || (id == RTE_TRAP_I_ACCESS) || (id == RTE_TRAP_I_ILLEGAL) ||
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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switch (trap_cause) {
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switch (trap_cause) {
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
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case TRAP_CODE_I_MISALIGNED: neorv32_uart_printf("Instruction address misaligned"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart_printf("Instruction access fault"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart_printf("Illegal instruction"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart_printf("Breakpoint"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart_printf("Load address misaligned"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart_printf("Load access fault"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart_printf("Store address misaligned"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart_printf("Store access fault"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call from M-mode"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart_printf("Environment call"); break;
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case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
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case TRAP_CODE_MSI: neorv32_uart_printf("Machine software interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
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case TRAP_CODE_MTI: neorv32_uart_printf("Machine timer interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
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case TRAP_CODE_MEI: neorv32_uart_printf("Machine external interrupt"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt channel 0"); break;
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case TRAP_CODE_FIRQ_0: neorv32_uart_printf("Fast interrupt 0"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt channel 1"); break;
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case TRAP_CODE_FIRQ_1: neorv32_uart_printf("Fast interrupt 1"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt channel 2"); break;
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case TRAP_CODE_FIRQ_2: neorv32_uart_printf("Fast interrupt 2"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt channel 3"); break;
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case TRAP_CODE_FIRQ_3: neorv32_uart_printf("Fast interrupt 3"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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}
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}
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// address
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// address
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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