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[/] [neorv32/] [trunk/] [sw/] [lib/] [source/] [neorv32_rte.c] - Diff between revs 22 and 23

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Rev 22 Rev 23
Line 208... Line 208...
    case TRAP_CODE_S_ACCESS:     neorv32_uart_printf("Store access fault"); break;
    case TRAP_CODE_S_ACCESS:     neorv32_uart_printf("Store access fault"); break;
    case TRAP_CODE_MENV_CALL:    neorv32_uart_printf("Environment call"); break;
    case TRAP_CODE_MENV_CALL:    neorv32_uart_printf("Environment call"); break;
    case TRAP_CODE_MSI:          neorv32_uart_printf("Machine software interrupt"); break;
    case TRAP_CODE_MSI:          neorv32_uart_printf("Machine software interrupt"); break;
    case TRAP_CODE_MTI:          neorv32_uart_printf("Machine timer interrupt"); break;
    case TRAP_CODE_MTI:          neorv32_uart_printf("Machine timer interrupt"); break;
    case TRAP_CODE_MEI:          neorv32_uart_printf("Machine external interrupt"); break;
    case TRAP_CODE_MEI:          neorv32_uart_printf("Machine external interrupt"); break;
    case TRAP_CODE_FIRQ_0:       neorv32_uart_printf("Fast interrupt 0"); break;
    case TRAP_CODE_FIRQ_0:       neorv32_uart_printf("Fast interrupt 0 (WDT)"); break;
    case TRAP_CODE_FIRQ_1:       neorv32_uart_printf("Fast interrupt 1"); break;
    case TRAP_CODE_FIRQ_1:       neorv32_uart_printf("Fast interrupt 1 (GPIO)"); break;
    case TRAP_CODE_FIRQ_2:       neorv32_uart_printf("Fast interrupt 2"); break;
    case TRAP_CODE_FIRQ_2:       neorv32_uart_printf("Fast interrupt 2 (UART)"); break;
    case TRAP_CODE_FIRQ_3:       neorv32_uart_printf("Fast interrupt 3"); break;
    case TRAP_CODE_FIRQ_3:       neorv32_uart_printf("Fast interrupt 3 (SPI/TWI)"); break;
    default:                     neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
    default:                     neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
  }
  }
 
 
  // address
  // address
  register uint32_t trap_addr  = neorv32_cpu_csr_read(CSR_MEPC);
  register uint32_t trap_addr  = neorv32_cpu_csr_read(CSR_MEPC);
Line 247... Line 247...
  neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
  neorv32_uart_printf("\n\n<< NEORV32 Hardware Configuration Overview >>\n");
 
 
  // CPU configuration
  // CPU configuration
  neorv32_uart_printf("\n-- Central Processing Unit --\n");
  neorv32_uart_printf("\n-- Central Processing Unit --\n");
 
 
  // Hart ID
  // ID
  neorv32_uart_printf("Hart ID:          %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
  neorv32_uart_printf("Hart ID:          %u\n", neorv32_cpu_csr_read(CSR_MHARTID));
 
 
  // Custom user code
  neorv32_uart_printf("Vendor ID:        0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
  neorv32_uart_printf("User code:        0x%x\n", SYSINFO_USER_CODE);
 
 
  tmp = neorv32_cpu_csr_read(CSR_MARCHID);
 
  neorv32_uart_printf("Architecture ID:  0x%x", tmp);
 
 
 
  // Custom user code/ID
 
  neorv32_uart_printf("\nUser ID:          0x%x\n", SYSINFO_USER_CODE);
 
 
  // HW version
  // HW version
  neorv32_uart_printf("Hardware version: ");
  neorv32_uart_printf("Hardware version: ");
  neorv32_rte_print_hw_version();
  neorv32_rte_print_hw_version();
  neorv32_uart_printf(" (0x%x)\n", neorv32_cpu_csr_read(CSR_MIMPID));
 
 
 
  // CPU architecture
  // CPU architecture
  neorv32_uart_printf("Architecture:     ");
  neorv32_uart_printf("\nArchitecture:     ");
  tmp = neorv32_cpu_csr_read(CSR_MISA);
  tmp = neorv32_cpu_csr_read(CSR_MISA);
  tmp = (tmp >> 30) & 0x03;
  tmp = (tmp >> 30) & 0x03;
  if (tmp == 0) {
  if (tmp == 0) {
    neorv32_uart_printf("unknown");
    neorv32_uart_printf("unknown");
  }
  }
Line 276... Line 280...
  if (tmp == 3) {
  if (tmp == 3) {
    neorv32_uart_printf("RV128");
    neorv32_uart_printf("RV128");
  }
  }
 
 
  // CPU extensions
  // CPU extensions
  neorv32_uart_printf(" + ");
  neorv32_uart_printf("\nExtensions:       ");
  tmp = neorv32_cpu_csr_read(CSR_MISA);
  tmp = neorv32_cpu_csr_read(CSR_MISA);
  for (i=0; i<26; i++) {
  for (i=0; i<26; i++) {
    if (tmp & (1 << i)) {
    if (tmp & (1 << i)) {
      c = (char)('A' + i);
      c = (char)('A' + i);
      neorv32_uart_putc(c);
      neorv32_uart_putc(c);
      neorv32_uart_putc(' ');
      neorv32_uart_putc(' ');
    }
    }
  }
  }
  neorv32_uart_printf("(0x%x)\n", tmp);
 
 
 
  // Z* CPU extensions (from custom CSR)
  // Z* CPU extensions (from custom CSR "mzext")
  neorv32_uart_printf("Z* extensions:    ");
 
  tmp = neorv32_cpu_csr_read(CSR_MZEXT);
  tmp = neorv32_cpu_csr_read(CSR_MZEXT);
  if (tmp & (1<<0)) {
  if (tmp & (1<<0)) {
    neorv32_uart_printf("Zicsr ");
    neorv32_uart_printf("Zicsr ");
  }
  }
  if (tmp & (1<<1)) {
  if (tmp & (1<<1)) {
    neorv32_uart_printf("Zifencei ");
    neorv32_uart_printf("Zifencei ");
  }
  }
  if (tmp & (1<<2)) {
 
    neorv32_uart_printf("cpu_counters ");
 
  }
 
 
 
 
 
  // Misc
  // Misc
  neorv32_uart_printf("\n\n-- System --\n");
  neorv32_uart_printf("\n\n-- System --\n");
  neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
  neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
 
 
 
 
  // Memory configuration
  // Memory configuration
  neorv32_uart_printf("\n-- Processor Memory Configuration --\n");
  neorv32_uart_printf("\n-- Processor Memory Configuration --\n");
 
 
  uint32_t size = SYSINFO_ISPACE_SIZE;
  neorv32_uart_printf("Instr. base address:  0x%x\n", SYSINFO_ISPACE_BASE);
  uint32_t base = SYSINFO_ISPACE_BASE;
 
  neorv32_uart_printf("Instruction memory:   %u bytes @ 0x%x\n", size, base);
 
  neorv32_uart_printf("Internal IMEM:        ");
  neorv32_uart_printf("Internal IMEM:        ");
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM));
 
  neorv32_uart_printf("IMEM size:            %u bytes\n", SYSINFO_IMEM_SIZE);
  neorv32_uart_printf("Internal IMEM as ROM: ");
  neorv32_uart_printf("Internal IMEM as ROM: ");
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM));
 
 
  size = SYSINFO_DSPACE_SIZE;
  neorv32_uart_printf("Data base address:    0x%x\n", SYSINFO_DSPACE_BASE);
  base = SYSINFO_DSPACE_BASE;
 
  neorv32_uart_printf("Data memory:          %u bytes @ 0x%x\n", size, base);
 
  neorv32_uart_printf("Internal DMEM:        ");
  neorv32_uart_printf("Internal DMEM:        ");
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM));
 
  neorv32_uart_printf("DMEM size:            %u bytes\n", SYSINFO_DMEM_SIZE);
 
 
  neorv32_uart_printf("Bootloader:           ");
  neorv32_uart_printf("Bootloader:           ");
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
  __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
 
 
  neorv32_uart_printf("External interface:   ");
  neorv32_uart_printf("External interface:   ");
Line 360... Line 357...
  neorv32_uart_printf("TRNG:    ");
  neorv32_uart_printf("TRNG:    ");
  __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
  __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
 
 
  neorv32_uart_printf("DEVNULL: ");
  neorv32_uart_printf("DEVNULL: ");
  __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
  __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_DEVNULL));
 
 
 
  neorv32_uart_printf("CFU:     ");
 
  __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFU));
}
}
 
 
 
 
/**********************************************************************//**
/**********************************************************************//**
 * NEORV32 runtime environment: Private function to print true or false.
 * NEORV32 runtime environment: Private function to print true or false.

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