| Line 53... |
Line 53... |
static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_true_false(int state) __attribute__((unused));
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static void __neorv32_rte_print_hex_word(uint32_t num);
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static void __neorv32_rte_print_hex_word(uint32_t num);
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/**********************************************************************//**
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/**********************************************************************//**
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* Floating-Point extension notifier.
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**************************************************************************/
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#ifdef __riscv_flen
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#warning Floating-point extension <F> is WORK-IN-PROGRESS and NOT FULLY OPERATIONAL yet!
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#endif
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/**********************************************************************//**
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* Setup NEORV32 runtime environment.
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* Setup NEORV32 runtime environment.
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*
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*
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* @note This function installs a debug handler for ALL exception and interrupt sources, which
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* @note This function installs a debug handler for ALL exception and interrupt sources, which
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* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
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Line 345... |
neorv32_uart_printf("Zbb ");
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neorv32_uart_printf("Zbb ");
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}
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}
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if (tmp & (1<<CSR_MZEXT_ZBS)) {
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if (tmp & (1<<CSR_MZEXT_ZBS)) {
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neorv32_uart_printf("Zbs ");
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neorv32_uart_printf("Zbs ");
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}
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}
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if (tmp & (1<<CSR_MZEXT_ZBA)) {
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neorv32_uart_printf("Zba ");
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}
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if (tmp & (1<<CSR_MZEXT_ZFINX)) {
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neorv32_uart_printf("Zfinx ");
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}
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// check physical memory protection
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// check physical memory protection
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neorv32_uart_printf("\nPMP: ");
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neorv32_uart_printf("\nPMP: ");
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uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
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uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
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if (pmp_num_regions != 0) {
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if (pmp_num_regions != 0) {
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Line 643... |
**************************************************************************/
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**************************************************************************/
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uint32_t neorv32_rte_get_compiler_isa(void) {
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uint32_t neorv32_rte_get_compiler_isa(void) {
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uint32_t misa_cc = 0;
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uint32_t misa_cc = 0;
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#ifdef __riscv_atomic
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#if defined __riscv_atomic || defined __riscv_a
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misa_cc |= 1 << CSR_MISA_A_EXT;
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misa_cc |= 1 << CSR_MISA_A_EXT;
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#endif
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#endif
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#ifdef __riscv_compressed
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#ifdef __riscv_b
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misa_cc |= 1 << CSR_MISA_B_EXT;
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#endif
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#if defined __riscv_compressed || defined __riscv_c
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misa_cc |= 1 << CSR_MISA_C_EXT;
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misa_cc |= 1 << CSR_MISA_C_EXT;
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#endif
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#endif
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#if (__riscv_flen == 64)
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#if (__riscv_flen == 64) || defined __riscv_d
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misa_cc |= 1 << CSR_MISA_D_EXT;
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misa_cc |= 1 << CSR_MISA_D_EXT;
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#endif
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#endif
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#ifdef __riscv_32e
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#ifdef __riscv_32e
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misa_cc |= 1 << CSR_MISA_E_EXT;
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misa_cc |= 1 << CSR_MISA_E_EXT;
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#else
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#else
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misa_cc |= 1 << CSR_MISA_I_EXT;
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misa_cc |= 1 << CSR_MISA_I_EXT;
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#endif
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#endif
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#if (__riscv_flen == 32)
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#if (__riscv_flen == 32) || defined __riscv_f
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misa_cc |= 1 << CSR_MISA_F_EXT;
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misa_cc |= 1 << CSR_MISA_F_EXT;
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#endif
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#endif
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#ifdef __riscv_mul
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#if defined __riscv_mul || defined __riscv_m
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misa_cc |= 1 << CSR_MISA_M_EXT;
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misa_cc |= 1 << CSR_MISA_M_EXT;
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#endif
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#endif
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#if (__riscv_xlen == 32)
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#if (__riscv_xlen == 32)
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misa_cc |= 1 << CSR_MISA_MXL_LO_EXT;
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misa_cc |= 1 << CSR_MISA_MXL_LO_EXT;
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