| Line 61... |
Line 61... |
* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
|
* gives detailed information about the exception/interrupt. Actual handler can be installed afterwards
|
* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
|
* via neorv32_rte_exception_install(uint8_t id, void (*handler)(void)).
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_rte_setup(void) {
|
void neorv32_rte_setup(void) {
|
|
|
// check if CSR system is available at all
|
|
if (neorv32_cpu_csr_read(CSR_MISA) == 0) {
|
|
neorv32_uart_print("<RTE> WARNING! CPU CSR system not available! </RTE>");
|
|
}
|
|
|
|
// configure trap handler base address
|
// configure trap handler base address
|
uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
|
uint32_t mtvec_base = (uint32_t)(&__neorv32_rte_core);
|
neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
|
neorv32_cpu_csr_write(CSR_MTVEC, mtvec_base);
|
|
|
// install debug handler for all sources
|
// install debug handler for all sources
|
| Line 135... |
Line 130... |
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
|
register uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
|
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
|
neorv32_cpu_csr_write(CSR_MSCRATCH, rte_mepc); // store for later
|
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
|
register uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
|
|
|
// compute return address
|
// compute return address
|
if ((rte_mcause & 0x80000000) == 0) { // modify pc only if exception
|
if (((int32_t)rte_mcause) >= 0) { // modify pc only if exception (MSB cleared)
|
|
|
// get low half word of faulting instruction
|
// get low half word of faulting instruction
|
register uint32_t rte_trap_inst;
|
register uint32_t rte_trap_inst;
|
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
|
asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (rte_trap_inst) : [input_i] "r" (rte_mepc));
|
|
|
| Line 201... |
Line 196... |
* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
|
* NEORV32 runtime environment: Debug exception handler, printing various exception/interrupt information via UART.
|
* @note This function is used by neorv32_rte_exception_uninstall(void) only.
|
* @note This function is used by neorv32_rte_exception_uninstall(void) only.
|
**************************************************************************/
|
**************************************************************************/
|
static void __neorv32_rte_debug_exc_handler(void) {
|
static void __neorv32_rte_debug_exc_handler(void) {
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // handler cannot output anything if UART0 is not implemented
|
|
}
|
|
|
char tmp;
|
char tmp;
|
|
|
// intro
|
// intro
|
neorv32_uart_print("<RTE> ");
|
neorv32_uart_print("<RTE> ");
|
|
|
| Line 264... |
Line 263... |
/**********************************************************************//**
|
/**********************************************************************//**
|
* NEORV32 runtime environment: Print hardware configuration information via UART
|
* NEORV32 runtime environment: Print hardware configuration information via UART
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_rte_print_hw_config(void) {
|
void neorv32_rte_print_hw_config(void) {
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
uint32_t tmp;
|
uint32_t tmp;
|
int i;
|
int i;
|
char c;
|
char c;
|
|
|
neorv32_uart_printf("\n\n<<< Processor Configuration Overview >>>\n");
|
neorv32_uart_printf("\n\n<<< Processor Configuration Overview >>>\n");
|
|
|
// Processor - general stuff
|
// Processor - general stuff
|
neorv32_uart_printf("\n=== << General >> ===\n");
|
neorv32_uart0_printf("\n=== << General >> ===\n"
|
neorv32_uart_printf("Clock: %u Hz\n", SYSINFO_CLK);
|
"Clock: %u Hz\n"
|
neorv32_uart_printf("User ID: 0x%x\n", SYSINFO_USER_CODE);
|
"User ID: 0x%x\n", SYSINFO_CLK, SYSINFO_USER_CODE);
|
neorv32_uart_printf("Full HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET));
|
neorv32_uart0_printf("Full HW reset: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_HW_RESET));
|
neorv32_uart_printf("On-chip debug: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_OCD));
|
neorv32_uart0_printf("Boot Config.: Boot ");
|
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER)) {
|
|
neorv32_uart0_printf("via Bootloader\n");
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("from memory (@ 0x%x)\n", SYSINFO_ISPACE_BASE);
|
|
}
|
|
neorv32_uart0_printf("On-chip debug: "); __neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_OCD));
|
|
|
|
|
// CPU configuration
|
// CPU configuration
|
neorv32_uart_printf("\n=== << CPU >> ===\n");
|
neorv32_uart0_printf("\n=== << CPU >> ===\n");
|
|
|
// ID
|
// ID
|
neorv32_uart_printf("Hart ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID));
|
neorv32_uart0_printf("Hart ID: 0x%x\n"
|
neorv32_uart_printf("Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MVENDORID));
|
"Vendor ID: 0x%x\n", neorv32_cpu_csr_read(CSR_MHARTID), neorv32_cpu_csr_read(CSR_MVENDORID));
|
|
|
tmp = neorv32_cpu_csr_read(CSR_MARCHID);
|
tmp = neorv32_cpu_csr_read(CSR_MARCHID);
|
neorv32_uart_printf("Architecture ID: 0x%x", tmp);
|
neorv32_uart0_printf("Architecture ID: 0x%x", tmp);
|
if (tmp == NEORV32_ARCHID) {
|
if (tmp == NEORV32_ARCHID) {
|
neorv32_uart_printf(" (NEORV32)");
|
neorv32_uart0_printf(" (NEORV32)");
|
}
|
}
|
|
|
// hardware version
|
// hardware version
|
neorv32_uart_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
|
neorv32_uart0_printf("\nImplementation ID: 0x%x (", neorv32_cpu_csr_read(CSR_MIMPID));
|
neorv32_rte_print_hw_version();
|
neorv32_rte_print_hw_version();
|
neorv32_uart_putc(')');
|
neorv32_uart0_putc(')');
|
|
|
// CPU architecture and endianness
|
// CPU architecture and endianness
|
neorv32_uart_printf("\nArchitecture: ");
|
neorv32_uart0_printf("\nArchitecture: ");
|
tmp = neorv32_cpu_csr_read(CSR_MISA);
|
tmp = neorv32_cpu_csr_read(CSR_MISA);
|
tmp = (tmp >> 30) & 0x03;
|
tmp = (tmp >> 30) & 0x03;
|
if (tmp == 1) {
|
if (tmp == 1) {
|
neorv32_uart_printf("rv32-little");
|
neorv32_uart0_printf("rv32-little");
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("unknown");
|
neorv32_uart0_printf("unknown");
|
}
|
}
|
|
|
// CPU extensions
|
// CPU extensions
|
neorv32_uart_printf("\nExtensions: ");
|
neorv32_uart0_printf("\nISA extensions: ");
|
tmp = neorv32_cpu_csr_read(CSR_MISA);
|
tmp = neorv32_cpu_csr_read(CSR_MISA);
|
for (i=0; i<26; i++) {
|
for (i=0; i<26; i++) {
|
if (tmp & (1 << i)) {
|
if (tmp & (1 << i)) {
|
c = (char)('A' + i);
|
c = (char)('A' + i);
|
neorv32_uart_putc(c);
|
neorv32_uart0_putc(c);
|
neorv32_uart_putc(' ');
|
neorv32_uart0_putc(' ');
|
}
|
}
|
}
|
}
|
|
|
// Z* CPU extensions (from custom "mzext" CSR)
|
// Z* CPU extensions (from custom "mzext" CSR)
|
tmp = neorv32_cpu_csr_read(CSR_MZEXT);
|
tmp = neorv32_cpu_csr_read(CSR_MZEXT);
|
if (tmp & (1<<CSR_MZEXT_ZICSR)) {
|
if (tmp & (1<<CSR_MZEXT_ZICSR)) {
|
neorv32_uart_printf("Zicsr ");
|
neorv32_uart0_printf("Zicsr ");
|
}
|
}
|
if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
|
if (tmp & (1<<CSR_MZEXT_ZIFENCEI)) {
|
neorv32_uart_printf("Zifencei ");
|
neorv32_uart0_printf("Zifencei ");
|
|
}
|
|
if (tmp & (1<<CSR_MZEXT_ZMMUL)) {
|
|
neorv32_uart0_printf("Zmmul ");
|
}
|
}
|
|
|
if (tmp & (1<<CSR_MZEXT_ZFINX)) {
|
if (tmp & (1<<CSR_MZEXT_ZFINX)) {
|
neorv32_uart_printf("Zfinx ");
|
neorv32_uart0_printf("Zfinx ");
|
}
|
}
|
if (tmp & (1<<CSR_MZEXT_ZXNOCNT)) {
|
if (tmp & (1<<CSR_MZEXT_ZXNOCNT)) {
|
neorv32_uart_printf("Zxnocnt(!) ");
|
neorv32_uart0_printf("Zxnocnt(!) ");
|
}
|
}
|
if (tmp & (1<<CSR_MZEXT_ZXSCNT)) {
|
if (tmp & (1<<CSR_MZEXT_ZXSCNT)) {
|
neorv32_uart_printf("Zxscnt(!) ");
|
neorv32_uart0_printf("Zxscnt(!) ");
|
}
|
}
|
if (tmp & (1<<CSR_MZEXT_DEBUGMODE)) {
|
if (tmp & (1<<CSR_MZEXT_DEBUGMODE)) {
|
neorv32_uart_printf("Debug-Mode ");
|
neorv32_uart0_printf("Debug-Mode ");
|
}
|
}
|
|
|
// check physical memory protection
|
// check physical memory protection
|
neorv32_uart_printf("\nPMP: ");
|
neorv32_uart0_printf("\nPMP: ");
|
uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
|
uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
|
if (pmp_num_regions != 0) {
|
if (pmp_num_regions != 0) {
|
neorv32_uart_printf("%u regions, %u bytes minimal granularity\n", pmp_num_regions, neorv32_cpu_pmp_get_granularity());
|
neorv32_uart0_printf("%u regions, %u bytes minimal granularity\n", pmp_num_regions, neorv32_cpu_pmp_get_granularity());
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("not implemented\n");
|
neorv32_uart0_printf("not implemented\n");
|
}
|
}
|
|
|
// check hardware performance monitors
|
// check hardware performance monitors
|
neorv32_uart_printf("HPM Counters: %u counters, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
|
neorv32_uart0_printf("HPM Counters: %u counters, %u-bit wide\n", neorv32_cpu_hpm_get_counters(), neorv32_cpu_hpm_get_size());
|
|
|
|
|
// Memory configuration
|
// Memory configuration
|
neorv32_uart_printf("\n=== << Memory Configuration >> ===\n");
|
neorv32_uart0_printf("\n=== << Memory Configuration >> ===\n");
|
|
|
neorv32_uart_printf("Instr. base address: 0x%x\n", SYSINFO_ISPACE_BASE);
|
neorv32_uart0_printf("Instr. base address: 0x%x\n", SYSINFO_ISPACE_BASE);
|
|
|
// IMEM
|
// IMEM
|
neorv32_uart_printf("Internal IMEM: ");
|
neorv32_uart0_printf("Internal IMEM: ");
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM)) {
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM)) {
|
neorv32_uart_printf("yes, %u bytes", SYSINFO_IMEM_SIZE);
|
neorv32_uart0_printf("yes, %u bytes\n", SYSINFO_IMEM_SIZE);
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_IMEM_ROM)) {
|
|
neorv32_uart_printf(", read-only (ROM)");
|
|
}
|
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("no");
|
neorv32_uart0_printf("no\n");
|
}
|
}
|
neorv32_uart_printf("\n");
|
|
|
|
// DMEM
|
// DMEM
|
neorv32_uart_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE);
|
neorv32_uart0_printf("Data base address: 0x%x\n", SYSINFO_DSPACE_BASE);
|
neorv32_uart_printf("Internal DMEM: ");
|
neorv32_uart0_printf("Internal DMEM: ");
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM)) { neorv32_uart_printf("yes, %u bytes\n", SYSINFO_DMEM_SIZE); }
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_INT_DMEM)) { neorv32_uart0_printf("yes, %u bytes\n", SYSINFO_DMEM_SIZE); }
|
else { neorv32_uart_printf("no\n"); }
|
else { neorv32_uart0_printf("no\n"); }
|
|
|
// i-cache
|
// i-cache
|
neorv32_uart_printf("Internal i-cache: ");
|
neorv32_uart0_printf("Internal i-cache: ");
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE));
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE));
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) {
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_ICACHE)) {
|
neorv32_uart_printf("- ");
|
neorv32_uart0_printf("- ");
|
|
|
uint32_t ic_block_size = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_BLOCK_SIZE_0) & 0x0F;
|
uint32_t ic_block_size = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_BLOCK_SIZE_0) & 0x0F;
|
if (ic_block_size) {
|
if (ic_block_size) {
|
ic_block_size = 1 << ic_block_size;
|
ic_block_size = 1 << ic_block_size;
|
}
|
}
|
| Line 403... |
Line 412... |
}
|
}
|
|
|
uint32_t ic_associativity = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_ASSOCIATIVITY_0) & 0x0F;
|
uint32_t ic_associativity = (SYSINFO_CACHE >> SYSINFO_CACHE_IC_ASSOCIATIVITY_0) & 0x0F;
|
ic_associativity = 1 << ic_associativity;
|
ic_associativity = 1 << ic_associativity;
|
|
|
neorv32_uart_printf("%u bytes: %u set(s), %u block(s) per set, %u bytes per block", ic_associativity*ic_num_blocks*ic_block_size, ic_associativity, ic_num_blocks, ic_block_size);
|
neorv32_uart0_printf("%u bytes: %u set(s), %u block(s) per set, %u bytes per block", ic_associativity*ic_num_blocks*ic_block_size, ic_associativity, ic_num_blocks, ic_block_size);
|
if (ic_associativity == 1) {
|
if (ic_associativity == 1) {
|
neorv32_uart_printf(" (direct-mapped)\n");
|
neorv32_uart0_printf(" (direct-mapped)\n");
|
}
|
}
|
else if (((SYSINFO_CACHE >> SYSINFO_CACHE_IC_REPLACEMENT_0) & 0x0F) == 1) {
|
else if (((SYSINFO_CACHE >> SYSINFO_CACHE_IC_REPLACEMENT_0) & 0x0F) == 1) {
|
neorv32_uart_printf(" (LRU replacement policy)\n");
|
neorv32_uart0_printf(" (LRU replacement policy)\n");
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("\n");
|
neorv32_uart0_printf("\n");
|
}
|
}
|
}
|
}
|
|
|
neorv32_uart_printf("Bootloader: ");
|
neorv32_uart0_printf("Ext. bus interface: ");
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_BOOTLOADER));
|
|
|
|
neorv32_uart_printf("Ext. bus interface: ");
|
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
|
__neorv32_rte_print_true_false(SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT));
|
neorv32_uart_printf("Ext. bus Endianness: ");
|
neorv32_uart0_printf("Ext. bus Endianness: ");
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT_ENDIAN)) {
|
if (SYSINFO_FEATURES & (1 << SYSINFO_FEATURES_MEM_EXT_ENDIAN)) {
|
neorv32_uart_printf("big\n");
|
neorv32_uart0_printf("big\n");
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("little\n");
|
neorv32_uart0_printf("little\n");
|
}
|
}
|
|
|
// peripherals
|
// peripherals
|
neorv32_uart_printf("\n=== << Peripherals >> ===\n");
|
neorv32_uart0_printf("\n=== << Peripherals >> ===\n");
|
|
|
tmp = SYSINFO_FEATURES;
|
tmp = SYSINFO_FEATURES;
|
|
neorv32_uart0_printf("GPIO - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
|
neorv32_uart_printf("GPIO - ");
|
neorv32_uart0_printf("MTIME - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_GPIO));
|
neorv32_uart0_printf("UART0 - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART0));
|
|
neorv32_uart0_printf("UART1 - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART1));
|
neorv32_uart_printf("MTIME - ");
|
neorv32_uart0_printf("SPI - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_MTIME));
|
neorv32_uart0_printf("TWI - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
|
|
neorv32_uart0_printf("PWM - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
|
neorv32_uart_printf("UART0 - ");
|
neorv32_uart0_printf("WDT - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART0));
|
neorv32_uart0_printf("TRNG - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
|
|
neorv32_uart0_printf("CFS - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFS));
|
neorv32_uart_printf("UART1 - ");
|
neorv32_uart0_printf("SLINK - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SLINK));
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_UART1));
|
neorv32_uart0_printf("NEOLED - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_NEOLED));
|
|
neorv32_uart0_printf("XIRQ - "); __neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_XIRQ));
|
neorv32_uart_printf("SPI - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_SPI));
|
|
|
|
neorv32_uart_printf("TWI - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TWI));
|
|
|
|
neorv32_uart_printf("PWM - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_PWM));
|
|
|
|
neorv32_uart_printf("WDT - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_WDT));
|
|
|
|
neorv32_uart_printf("TRNG - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_TRNG));
|
|
|
|
neorv32_uart_printf("CFS - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_CFS));
|
|
|
|
neorv32_uart_printf("NCO - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_NCO));
|
|
|
|
neorv32_uart_printf("NEOLED - ");
|
|
__neorv32_rte_print_true_false(tmp & (1 << SYSINFO_FEATURES_IO_NEOLED));
|
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* NEORV32 runtime environment: Private function to print yes or no.
|
* NEORV32 runtime environment: Private function to print yes or no.
|
| Line 480... |
Line 463... |
* @param[in] state Print 'yes' when !=0, print '0' when 0
|
* @param[in] state Print 'yes' when !=0, print '0' when 0
|
**************************************************************************/
|
**************************************************************************/
|
static void __neorv32_rte_print_true_false(int state) {
|
static void __neorv32_rte_print_true_false(int state) {
|
|
|
if (state) {
|
if (state) {
|
neorv32_uart_print("yes\n");
|
neorv32_uart0_print("yes\n");
|
}
|
}
|
else {
|
else {
|
neorv32_uart_print("no\n");
|
neorv32_uart0_print("no\n");
|
}
|
}
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 498... |
Line 481... |
**************************************************************************/
|
**************************************************************************/
|
void __neorv32_rte_print_hex_word(uint32_t num) {
|
void __neorv32_rte_print_hex_word(uint32_t num) {
|
|
|
static const char hex_symbols[16] = "0123456789ABCDEF";
|
static const char hex_symbols[16] = "0123456789ABCDEF";
|
|
|
neorv32_uart_print("0x");
|
neorv32_uart0_print("0x");
|
|
|
int i;
|
int i;
|
for (i=0; i<8; i++) {
|
for (i=0; i<8; i++) {
|
uint32_t index = (num >> (28 - 4*i)) & 0xF;
|
uint32_t index = (num >> (28 - 4*i)) & 0xF;
|
neorv32_uart_putc(hex_symbols[index]);
|
neorv32_uart0_putc(hex_symbols[index]);
|
}
|
}
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
| Line 516... |
Line 499... |
void neorv32_rte_print_hw_version(void) {
|
void neorv32_rte_print_hw_version(void) {
|
|
|
uint32_t i;
|
uint32_t i;
|
char tmp, cnt;
|
char tmp, cnt;
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
for (i=0; i<4; i++) {
|
for (i=0; i<4; i++) {
|
|
|
tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
|
tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
|
|
|
// serial division
|
// serial division
|
| Line 528... |
Line 515... |
tmp = tmp - 16;
|
tmp = tmp - 16;
|
cnt++;
|
cnt++;
|
}
|
}
|
|
|
if (cnt) {
|
if (cnt) {
|
neorv32_uart_putc('0' + cnt);
|
neorv32_uart0_putc('0' + cnt);
|
}
|
}
|
neorv32_uart_putc('0' + tmp);
|
neorv32_uart0_putc('0' + tmp);
|
if (i < 3) {
|
if (i < 3) {
|
neorv32_uart_putc('.');
|
neorv32_uart0_putc('.');
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* NEORV32 runtime environment: Print project credits
|
* NEORV32 runtime environment: Print project credits
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_rte_print_credits(void) {
|
void neorv32_rte_print_credits(void) {
|
|
|
neorv32_uart_print("The NEORV32 Processor Project\n"
|
if (neorv32_uart0_available() == 0) {
|
"Copyright 2021, Stephan Nolting\n"
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
|
neorv32_uart0_print("The NEORV32 RISC-V Processor\n"
|
|
"(c) Stephan Nolting\n"
|
"BSD 3-Clause License\n"
|
"BSD 3-Clause License\n"
|
"https://github.com/stnolting/neorv32\n\n");
|
"https://github.com/stnolting/neorv32\n\n");
|
}
|
}
|
|
|
|
|
| Line 573... |
Line 564... |
};
|
};
|
|
|
int u,v,w;
|
int u,v,w;
|
uint32_t tmp;
|
uint32_t tmp;
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
for (u=0; u<11; u++) {
|
for (u=0; u<11; u++) {
|
neorv32_uart_print("\n");
|
neorv32_uart0_print("\n");
|
for (v=0; v<4; v++) {
|
for (v=0; v<4; v++) {
|
tmp = logo_data_c[u][v];
|
tmp = logo_data_c[u][v];
|
for (w=0; w<32; w++){
|
for (w=0; w<32; w++){
|
if (tmp & 0x80000000UL) { // check MSB
|
if (((int32_t)tmp) < 0) { // check MSB
|
neorv32_uart_putc('#');
|
neorv32_uart0_putc('#');
|
}
|
}
|
else {
|
else {
|
neorv32_uart_putc(' ');
|
neorv32_uart0_putc(' ');
|
}
|
}
|
tmp <<= 1;
|
tmp <<= 1;
|
}
|
}
|
}
|
}
|
}
|
}
|
neorv32_uart_print("\n");
|
neorv32_uart0_print("\n");
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* NEORV32 runtime environment: Print project license
|
* NEORV32 runtime environment: Print project license
|
**************************************************************************/
|
**************************************************************************/
|
void neorv32_rte_print_license(void) {
|
void neorv32_rte_print_license(void) {
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
neorv32_uart_print(
|
neorv32_uart_print(
|
"\n"
|
"\n"
|
"BSD 3-Clause License\n"
|
"BSD 3-Clause License\n"
|
"\n"
|
"\n"
|
"Copyright (c) 2021, Stephan Nolting. All rights reserved.\n"
|
"Copyright (c) 2021, Stephan Nolting. All rights reserved.\n"
|
| Line 642... |
Line 641... |
uint32_t neorv32_rte_get_compiler_isa(void) {
|
uint32_t neorv32_rte_get_compiler_isa(void) {
|
|
|
uint32_t misa_cc = 0;
|
uint32_t misa_cc = 0;
|
|
|
#if defined __riscv_atomic || defined __riscv_a
|
#if defined __riscv_atomic || defined __riscv_a
|
misa_cc |= 1 << CSR_MISA_A_EXT;
|
misa_cc |= 1 << CSR_MISA_A;
|
#endif
|
#endif
|
|
|
#ifdef __riscv_b
|
#ifdef __riscv_b
|
misa_cc |= 1 << CSR_MISA_B_EXT;
|
misa_cc |= 1 << CSR_MISA_B;
|
#endif
|
#endif
|
|
|
#if defined __riscv_compressed || defined __riscv_c
|
#if defined __riscv_compressed || defined __riscv_c
|
misa_cc |= 1 << CSR_MISA_C_EXT;
|
misa_cc |= 1 << CSR_MISA_C;
|
#endif
|
#endif
|
|
|
#if (__riscv_flen == 64) || defined __riscv_d
|
#if (__riscv_flen == 64) || defined __riscv_d
|
misa_cc |= 1 << CSR_MISA_D_EXT;
|
misa_cc |= 1 << CSR_MISA_D;
|
#endif
|
#endif
|
|
|
#ifdef __riscv_32e
|
#ifdef __riscv_32e
|
misa_cc |= 1 << CSR_MISA_E_EXT;
|
misa_cc |= 1 << CSR_MISA_E;
|
#else
|
#else
|
misa_cc |= 1 << CSR_MISA_I_EXT;
|
misa_cc |= 1 << CSR_MISA_I;
|
#endif
|
#endif
|
|
|
#if (__riscv_flen == 32) || defined __riscv_f
|
#if (__riscv_flen == 32) || defined __riscv_f
|
misa_cc |= 1 << CSR_MISA_F_EXT;
|
misa_cc |= 1 << CSR_MISA_F;
|
#endif
|
#endif
|
|
|
#if defined __riscv_mul || defined __riscv_m
|
#if defined __riscv_mul || defined __riscv_m
|
misa_cc |= 1 << CSR_MISA_M_EXT;
|
misa_cc |= 1 << CSR_MISA_M;
|
#endif
|
#endif
|
|
|
#if (__riscv_xlen == 32)
|
#if (__riscv_xlen == 32)
|
misa_cc |= 1 << CSR_MISA_MXL_LO_EXT;
|
misa_cc |= 1 << CSR_MISA_MXL_LO;
|
#elif (__riscv_xlen == 64)
|
#elif (__riscv_xlen == 64)
|
misa_cc |= 2 << CSR_MISA_MXL_LO_EXT;
|
misa_cc |= 2 << CSR_MISA_MXL_LO;
|
#else
|
#else
|
misa_cc |= 3 << CSR_MISA_MXL_LO_EXT;
|
misa_cc |= 3 << CSR_MISA_MXL_LO;
|
#endif
|
#endif
|
|
|
return misa_cc;
|
return misa_cc;
|
}
|
}
|
|
|
| Line 702... |
Line 701... |
//
|
//
|
if (check == misa_sw) {
|
if (check == misa_sw) {
|
return 0;
|
return 0;
|
}
|
}
|
else {
|
else {
|
if (silent == 0) {
|
if ((silent == 0) || (neorv32_uart0_available() == 0)) {
|
neorv32_uart_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
|
neorv32_uart_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
|
"SW_ISA = 0x%x (compiler flags)\n"
|
"SW_ISA = 0x%x (compiler flags)\n"
|
"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
|
"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
|
}
|
}
|
return 1;
|
return 1;
|
