| Line 155... |
Line 155... |
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neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");
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neorv32_uart_printf("\n\n<< NEORV32 Runtime Environment >>\n");
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neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));
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neorv32_uart_printf("System time: 0x%x_%x\n", neorv32_cpu_csr_read(CSR_TIMEH), neorv32_cpu_csr_read(CSR_TIME));
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register uint32_t exc_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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register uint32_t return_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trap_addr = neorv32_cpu_csr_read(CSR_MEPC);
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register uint32_t trans_cmd = neorv32_cpu_csr_read(CSR_MTINST);
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register uint32_t trap_inst;
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if (exc_cause & 0x80000000) {
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// get faulting instruction
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asm volatile ("lh %[result], 0(%[input_i])" : [result] "=r" (trap_inst) : [input_i] "r" (trap_addr));
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if (trap_cause & 0x80000000) {
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neorv32_uart_printf("INTERRUPT");
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neorv32_uart_printf("INTERRUPT");
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}
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}
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else {
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else {
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neorv32_uart_printf("EXCEPTION");
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neorv32_uart_printf("EXCEPTION");
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if ((trans_cmd & (1 << 1)) == 0) {
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if ((trap_inst & 3) == 3) {
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return_addr -= 4;
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trap_addr -= 4;
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}
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}
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else {
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else {
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return_addr -= 2;
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trap_addr -= 2;
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}
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}
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}
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}
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neorv32_uart_printf(" at instruction address: 0x%x\n", return_addr);
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neorv32_uart_printf(" at instruction address: 0x%x\n", trap_addr);
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neorv32_uart_printf("Cause: ");
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neorv32_uart_printf("Cause: ");
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switch (exc_cause) {
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switch (trap_cause) {
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case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break;
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case 0x00000000: neorv32_uart_printf("Instruction address misaligned"); break;
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case 0x00000001: neorv32_uart_printf("Instruction access fault"); break;
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case 0x00000001: neorv32_uart_printf("Instruction access fault"); break;
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case 0x00000002: neorv32_uart_printf("Illegal instruction"); break;
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case 0x00000002: neorv32_uart_printf("Illegal instruction"); break;
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case 0x00000003: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
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case 0x00000003: neorv32_uart_printf("Breakpoint (EBREAK)"); break;
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case 0x00000004: neorv32_uart_printf("Load address misaligned"); break;
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case 0x00000004: neorv32_uart_printf("Load address misaligned"); break;
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| Line 187... |
Line 190... |
case 0x00000007: neorv32_uart_printf("Store access fault"); break;
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case 0x00000007: neorv32_uart_printf("Store access fault"); break;
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case 0x0000000B: neorv32_uart_printf("Environment call (ECALL)"); break;
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case 0x0000000B: neorv32_uart_printf("Environment call (ECALL)"); break;
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case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break;
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case 0x80000003: neorv32_uart_printf("Machine software interrupt"); break;
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case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break;
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case 0x80000007: neorv32_uart_printf("Machine timer interrupt (via MTIME)"); break;
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case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;
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case 0x8000000B: neorv32_uart_printf("Machine external interrupt (via CLIC)"); break;
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default: neorv32_uart_printf("Unknown (0x%x)", exc_cause); break;
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default: neorv32_uart_printf("Unknown (0x%x)", trap_cause); break;
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}
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}
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// fault address
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// fault address
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if (exc_cause == 0x00000002) {
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neorv32_uart_printf("\nFaulting instruction: 0x%x\n", trap_inst);
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neorv32_uart_printf("\nFaulting instruction");
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neorv32_uart_printf("MTVAL: 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
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}
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else {
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neorv32_uart_printf("\nFaulting address");
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}
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neorv32_uart_printf(": 0x%x\n", neorv32_cpu_csr_read(CSR_MTVAL));
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neorv32_uart_printf("Transf. instruction: 0x%x ", trans_cmd);
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if ((trans_cmd & (1 << 1)) == 0) {
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if ((trap_inst & 3) != 3) {
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neorv32_uart_printf("(decompressed)\n");
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neorv32_uart_printf("(decompressed)\n");
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}
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}
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neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
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neorv32_uart_printf("Trying to resume application @ 0x%x...", neorv32_cpu_csr_read(CSR_MEPC));
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