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Line 63... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum.
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* Enable and configure SPI controller. The SPI control register bits are listed in #NEORV32_SPI_CTRL_enum.
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*
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*
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] prsc Clock prescaler select (0..7). See #NEORV32_CLOCK_PRSC_enum.
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* @param[in] clk_polarity Idle clock polarity (0, 1).
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* @param[in] clk_phase Clock phase (0=sample on rising edge, 1=sample on falling edge).
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* @param[in] clk_polarity Clock polarity (when idle).
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* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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* @param[in] data_size Data transfer size (0: 8-bit, 1: 16-bit, 2: 24-bit, 3: 32-bit).
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**************************************************************************/
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**************************************************************************/
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void neorv32_spi_setup(uint8_t prsc, uint8_t clk_polarity, uint8_t data_size) {
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void neorv32_spi_setup(uint8_t prsc, uint8_t clk_phase, uint8_t clk_polarity, uint8_t data_size) {
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NEORV32_SPI.CTRL = 0; // reset
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NEORV32_SPI.CTRL = 0; // reset
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uint32_t ct_enable = 1;
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uint32_t ct_enable = 1;
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ct_enable = ct_enable << SPI_CTRL_EN;
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ct_enable = ct_enable << SPI_CTRL_EN;
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uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
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uint32_t ct_prsc = (uint32_t)(prsc & 0x07);
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ct_prsc = ct_prsc << SPI_CTRL_PRSC0;
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ct_prsc = ct_prsc << SPI_CTRL_PRSC0;
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uint32_t ct_phase = (uint32_t)(clk_phase & 0x01);
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ct_phase = ct_phase << SPI_CTRL_CPHA;
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uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
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uint32_t ct_polarity = (uint32_t)(clk_polarity & 0x01);
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ct_polarity = ct_polarity << SPI_CTRL_CPHA;
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ct_polarity = ct_polarity << SPI_CTRL_CPOL;
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uint32_t ct_size = (uint32_t)(data_size & 0x03);
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uint32_t ct_size = (uint32_t)(data_size & 0x03);
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ct_size = ct_size << SPI_CTRL_SIZE0;
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ct_size = ct_size << SPI_CTRL_SIZE0;
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NEORV32_SPI.CTRL = ct_enable | ct_prsc | ct_polarity | ct_size;
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NEORV32_SPI.CTRL = ct_enable | ct_prsc | ct_phase | ct_polarity | ct_size;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Disable SPI controller.
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* Disable SPI controller.
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Line 160... |
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/**********************************************************************//**
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/**********************************************************************//**
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* Check if SPI transceiver is busy.
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* Check if SPI transceiver is busy.
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*
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*
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* @note This function is blocking.
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*
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* @return 0 if idle, 1 if busy
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* @return 0 if idle, 1 if busy
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**************************************************************************/
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**************************************************************************/
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int neorv32_spi_busy(void) {
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int neorv32_spi_busy(void) {
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if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
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if ((NEORV32_SPI.CTRL & (1<<SPI_CTRL_BUSY)) != 0) {
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return 1;
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return 1;
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}
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}
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else {
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return 0;
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return 0;
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}
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}
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}
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No newline at end of file
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