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Line 85... |
input IFETCH,
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input IFETCH,
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input FLUSH,
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input FLUSH,
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input MREQ,
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input MREQ,
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input WR,
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input WR,
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input WORD,
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input WORD,
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input [19:0]ADDR,
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input [20:0]ADDR,
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input [19:0]IADDR,
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input [20:0]IADDR,
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output reg CE186, // CPU clock enable
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output reg CE186, // CPU clock enable
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input [31:0]RAM_DIN,
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input [31:0]RAM_DIN,
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output [31:0]RAM_DOUT,
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output [31:0]RAM_DOUT,
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output [17:0]RAM_ADDR,
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output [18:0]RAM_ADDR,
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output RAM_MREQ,
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output RAM_MREQ,
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output wire[3:0]RAM_WMASK,
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output wire[3:0]RAM_WMASK,
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output reg [15:0]DOUT,
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output reg [15:0]DOUT,
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input [15:0]DIN,
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input [15:0]DIN,
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input CE // BIU clock enable
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input CE, // BIU clock enable
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output reg data_bound,
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input [1:0]WSEL, // normally {~ADDR[0], ADDR[0]}
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output reg RAM_RD,
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output reg RAM_WR
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);
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);
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reg [31:0]queue[3:0];
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reg [31:0]queue[3:0];
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reg [1:0]STATE = 0;
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reg [1:0]STATE = 0;
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reg OLDSTATE = 1;
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reg OLDSTATE = 1;
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reg [3:0]qpos = 0;
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reg [3:0]qpos = 0;
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reg [4:0]qsize = 0;
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reg [4:0]qsize = 0;
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reg [1:0]rpos = 0;
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reg [1:0]rpos = 0;
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reg [17:0]piaddr = 0;
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reg [18:0]piaddr = 0;
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reg [7:0]exdata = 0;
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reg [7:0]exdata = 0;
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reg rdi = 0;
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reg rdi = 0;
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reg data_bound;
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reg [1:0]NEXTSTATE;
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reg [1:0]NEXTSTATE;
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reg RAM_RD;
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reg RAM_WR;
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reg sflush;
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reg sflush;
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wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;
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wire [4:0]newqsize = sflush ? -IADDR[1:0] : CE186 && IFETCH && ~FLUSH ? qsize - ISIZE : qsize;
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wire qnofull = qsize < 13;
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wire qnofull = qsize < 13;
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reg iread;// = (qnofull && !RAM_RD && !RAM_WR) || sflush;
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reg iread;// = (qnofull && !RAM_RD && !RAM_WR) || sflush;
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wire [3:0]nqpos = (FLUSH && IFETCH) ? {2'b00, IADDR[1:0]} : (qpos + ISIZE);
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wire [3:0]nqpos = (FLUSH && IFETCH) ? {2'b00, IADDR[1:0]} : (qpos + ISIZE);
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wire [17:0]MIADDR = sflush ? IADDR[19:2] : piaddr;
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wire [18:0]MIADDR = sflush ? IADDR[20:2] : piaddr;
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wire split = (&ADDR[1:0]) && WORD; // data between dwords
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wire split = (&ADDR[1:0]) && WORD; // data between dwords
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wire [15:0]DSWAP = ADDR[0] ? {DIN[7:0], DIN[15:8]} : DIN;
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wire [15:0]DSWAP = {WSEL[1] ? DIN[15:8] : DIN[7:0], WSEL[0] ? DIN[15:8] : DIN[7:0]}; //ADDR[0] ? {DIN[7:0], DIN[15:8]} : DIN;
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wire [1:0]a1 = nqpos[3:2] + 1;
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wire [1:0]a1 = nqpos[3:2] + 1;
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wire [1:0]a2 = nqpos[3:2] + 2;
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wire [1:0]a2 = nqpos[3:2] + 2;
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wire [31:0]q1 = rdi && (a1 == rpos) ? RAM_DIN : queue[a1];
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wire [31:0]q1 = rdi && (a1 == rpos) ? RAM_DIN : queue[a1];
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wire [7:0]q2 = rdi && (a2 == rpos) ? RAM_DIN[7:0] : queue[a2][7:0];
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wire [7:0]q2 = rdi && (a2 == rpos) ? RAM_DIN[7:0] : queue[a2][7:0];
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assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3'b000};
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assign INSTR = {q2, q1, queue[nqpos[3:2]]} >> {nqpos[1:0], 3'b000};
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// assign DOUT = split ? {RAM_DIN[7:0], exdata} : (RAM_DIN >> {ADDR[1:0], 3'b000});
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// assign DOUT = split ? {RAM_DIN[7:0], exdata} : (RAM_DIN >> {ADDR[1:0], 3'b000});
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assign RAM_DOUT = {DSWAP, DSWAP};
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assign RAM_DOUT = {DSWAP, DSWAP};
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assign RAM_MREQ = iread || RAM_RD || RAM_WR;
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assign RAM_MREQ = iread || RAM_RD || RAM_WR;
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assign RAM_ADDR = iread ? MIADDR : ADDR[19:2] + data_bound;
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assign RAM_ADDR = iread ? MIADDR : ADDR[20:2] + data_bound;
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assign RAM_WMASK = data_bound ? {3'b000, RAM_WR} : {2'b00, WORD & RAM_WR, RAM_WR} << ADDR[1:0];
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assign RAM_WMASK = data_bound ? {3'b000, RAM_WR} : {2'b00, WORD & RAM_WR, RAM_WR} << ADDR[1:0];
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always @(*) begin
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always @(*) begin
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RAM_RD = 0;
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RAM_RD = 0;
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RAM_WR = 0;
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RAM_WR = 0;
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