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https://opencores.org/ocsvn/next186/next186/trunk
[/] [next186/] [trunk/] [Next186_BIU_2T_delayread.v] - Diff between revs 19 and 20
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| Rev 19 |
Rev 20 |
| Line 99... |
Line 99... |
input [15:0]DIN,
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input [15:0]DIN,
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input CE, // BIU clock enable
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input CE, // BIU clock enable
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output reg data_bound,
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output reg data_bound,
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input [1:0]WSEL, // normally {~ADDR[0], ADDR[0]}
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input [1:0]WSEL, // normally {~ADDR[0], ADDR[0]}
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output reg RAM_RD,
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output reg RAM_RD,
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output reg RAM_WR
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output reg RAM_WR,
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input IORQ,
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input FASTIO
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);
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);
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reg [31:0]queue[3:0];
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reg [31:0]queue[3:0];
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reg [1:0]STATE = 0;
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reg [1:0]STATE = 0;
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reg OLDSTATE = 1;
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reg OLDSTATE = 1;
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| Line 171... |
Line 173... |
RAM_RD = 1;
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RAM_RD = 1;
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NEXTSTATE = split ? 2 : 3;
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NEXTSTATE = split ? 2 : 3;
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end
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end
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end else begin
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end else begin
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iread = qnofull;
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iread = qnofull;
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CE186 = 1;
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if(IORQ && !WR && !FASTIO) NEXTSTATE = 3;
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else CE186 = 1;
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end
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end
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end else iread = 1; // else nextstate = 1
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end else iread = 1; // else nextstate = 1
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end
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end
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2: begin
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2: begin
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RAM_RD = 1;
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RAM_RD = 1;
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