| Line 115... |
Line 115... |
wire [7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
|
wire [7:0]FlagMux = {FLAGS[7], !FLAGS[7], FLAGS[2], !FLAGS[2], FLAGS[0], !FLAGS[0], FLAGS[6], !FLAGS[6]};
|
reg tzf;
|
reg tzf;
|
reg SRESET = 0;
|
reg SRESET = 0;
|
reg SINT = 0;
|
reg SINT = 0;
|
|
|
Z80Reg CPU_REGS (
|
N8080_Reg CPU_REGS (
|
.rstatus(CPUStatus[0]),
|
.rstatus(CPUStatus[0]),
|
.M1(M1),
|
.M1(M1),
|
.WE(WE),
|
.WE(WE),
|
.CLK(CLK),
|
.CLK(CLK),
|
.ALU8OUT(ALU8OUT),
|
.ALU8OUT(ALU8OUT),
|
| Line 140... |
Line 140... |
.DINW_SEL(DINW_SEL),
|
.DINW_SEL(DINW_SEL),
|
.ALU16OP(ALU16OP), // used for post increment for ADDR, SP mux re-direct
|
.ALU16OP(ALU16OP), // used for post increment for ADDR, SP mux re-direct
|
.WAIT(WAIT)
|
.WAIT(WAIT)
|
);
|
);
|
|
|
ALU8 CPU_ALU8 (
|
N8080_ALU8 CPU_ALU8 (
|
.D0(ALU80),
|
.D0(ALU80),
|
.D1(ALU81),
|
.D1(ALU81),
|
.FIN(FLAGS),
|
.FIN(FLAGS),
|
.FOUT(ALU8FLAGS),
|
.FOUT(ALU8FLAGS),
|
.ALU8DOUT(ALU8OUT),
|
.ALU8DOUT(ALU8OUT),
|
.OP(ALU8OP)
|
.OP(ALU8OP)
|
);
|
);
|
|
|
ALU16 CPU_ALU16 (
|
N8080_ALU16 CPU_ALU16 (
|
.D0(ALU160),
|
.D0(ALU160),
|
.D1(ALU161),
|
.D1(ALU161),
|
.DOUT(ADDR),
|
.DOUT(ADDR),
|
.OP(ALU16OP)
|
.OP(ALU16OP)
|
);
|
);
|
| Line 981... |
Line 981... |
// 11010 - RLA D0
|
// 11010 - RLA D0
|
// 11011 - RRA D0
|
// 11011 - RRA D0
|
// 11101 - IN, pass D1
|
// 11101 - IN, pass D1
|
// 11110 - FLAGS <- D0
|
// 11110 - FLAGS <- D0
|
///////////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////////
|
module ALU8(
|
module N8080_ALU8(
|
input [7:0]D0,
|
input [7:0]D0,
|
input [7:0]D1,
|
input [7:0]D1,
|
input [7:0]FIN,
|
input [7:0]FIN,
|
input [4:0]OP,
|
input [4:0]OP,
|
|
|
| Line 1004... |
Line 1004... |
reg [3:0]logop;
|
reg [3:0]logop;
|
wire csin = OP[1] ? FIN[0] : OP[0] ? D0[0] : D0[7];
|
wire csin = OP[1] ? FIN[0] : OP[0] ? D0[0] : D0[7];
|
wire [7:0]shift = OP[0] ? {csin, D0[7:1]} : {D0[6:0], csin};
|
wire [7:0]shift = OP[0] ? {csin, D0[7:1]} : {D0[6:0], csin};
|
wire [15:0]inc16 = OP[0] ? {D0, D1} - 1'b1 : {D0, D1} + 1'b1;
|
wire [15:0]inc16 = OP[0] ? {D0, D1} - 1'b1 : {D0, D1} + 1'b1;
|
|
|
LOG8 log8_unit
|
N8080_LOG8 log8_unit
|
(
|
(
|
.A(D0),
|
.A(D0),
|
.B(D1),
|
.B(D1),
|
.O(log),
|
.O(log),
|
.op(logop)
|
.op(logop)
|
| Line 1080... |
Line 1080... |
default:;
|
default:;
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
endmodule
|
|
|
module LOG8(
|
module N8080_LOG8(
|
input [7:0]A,
|
input [7:0]A,
|
input [7:0]B,
|
input [7:0]B,
|
input [3:0]op, // 0=0, 1=~(A|B), 2=~A&B, 3=~A, 4=A&~B, 5=~B, 6=A^B, 7=~(A&B), 8=A&B, 9=~(A^B), 10=B, 11=~A|B, 12=A, 13=A|~B, 14=A|B, 15=-1
|
input [3:0]op, // 0=0, 1=~(A|B), 2=~A&B, 3=~A, 4=A&~B, 5=~B, 6=A^B, 7=~(A&B), 8=A&B, 9=~(A^B), 10=B, 11=~A|B, 12=A, 13=A|~B, 14=A|B, 15=-1
|
|
|
output [7:0]O
|
output [7:0]O
|
| Line 1098... |
Line 1098... |
assign O[5] = op[{A[5], B[5]}];
|
assign O[5] = op[{A[5], B[5]}];
|
assign O[6] = op[{A[6], B[6]}];
|
assign O[6] = op[{A[6], B[6]}];
|
assign O[7] = op[{A[7], B[7]}];
|
assign O[7] = op[{A[7], B[7]}];
|
endmodule
|
endmodule
|
|
|
module ALU16(
|
module N8080_ALU16(
|
input [15:0]D0,
|
input [15:0]D0,
|
input [7:0]D1,
|
input [7:0]D1,
|
input [2:0]OP, // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
|
input [2:0]OP, // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
|
|
|
output wire[15:0] DOUT
|
output wire[15:0] DOUT
|
| Line 1122... |
Line 1122... |
endcase
|
endcase
|
|
|
assign DOUT = D0 + {{8{mux[7]}}, mux};
|
assign DOUT = D0 + {{8{mux[7]}}, mux};
|
endmodule
|
endmodule
|
|
|
module Z80Reg(
|
module N8080_Reg(
|
input rstatus, // hl-de
|
input rstatus, // hl-de
|
input M1,
|
input M1,
|
input [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
|
input [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
|
input CLK,
|
input CLK,
|
input [15:0]ALU8OUT, // CPU data out bus (output of alu8)
|
input [15:0]ALU8OUT, // CPU data out bus (output of alu8)
|
| Line 1164... |
Line 1164... |
reg [15:0]DIN; // RAM W in data
|
reg [15:0]DIN; // RAM W in data
|
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
|
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
|
|
|
//------------------------------------ RAM block registers ----------------------------------
|
//------------------------------------ RAM block registers ----------------------------------
|
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:BC', 5:DE', 6:HL', 7:A'-x, 8:tmp
|
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:BC', 5:DE', 6:HL', 7:A'-x, 8:tmp
|
RAM16X8D_regs regs_lo (
|
N8080_RAM16X8D_regs regs_lo (
|
.DPO(rdor[7:0]), // Read-only data output
|
.DPO(rdor[7:0]), // Read-only data output
|
.SPO(rdow[7:0]), // R/W data output
|
.SPO(rdow[7:0]), // R/W data output
|
.A(SELW), // R/W address
|
.A(SELW), // R/W address
|
.D(DIN[7:0]), // Write data input
|
.D(DIN[7:0]), // Write data input
|
.DPRA(SELR), // Read-only address
|
.DPRA(SELR), // Read-only address
|
.WCLK(CLK), // Write clock input
|
.WCLK(CLK), // Write clock input
|
.WE(WE[0] & !WAIT) // Write enable input
|
.WE(WE[0] & !WAIT) // Write enable input
|
);
|
);
|
|
|
RAM16X8D_regs regs_hi (
|
N8080_RAM16X8D_regs regs_hi (
|
.DPO(rdor[15:8]), // Read-only data output
|
.DPO(rdor[15:8]), // Read-only data output
|
.SPO(rdow[15:8]), // R/W data output
|
.SPO(rdow[15:8]), // R/W data output
|
.A(SELW), // R/W address
|
.A(SELW), // R/W address
|
.D(DIN[15:8]), // Write data input
|
.D(DIN[15:8]), // Write data input
|
.DPRA(SELR), // Read-only address
|
.DPRA(SELR), // Read-only address
|
| Line 1219... |
Line 1219... |
5'b01100, 5'b01101, 5'b11100, 5'b11101: mux_rdor = {8'b0, CONST};
|
5'b01100, 5'b01101, 5'b11100, 5'b11101: mux_rdor = {8'b0, CONST};
|
default: mux_rdor = rdor;
|
default: mux_rdor = rdor;
|
endcase
|
endcase
|
end
|
end
|
|
|
RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus(rstatus));
|
N8080_RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus(rstatus));
|
RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus));
|
N8080_RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus));
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module RegSelect(
|
module N8080_RegSelect(
|
input [2:0]SEL,
|
input [2:0]SEL,
|
input rstatus, // 2=hl-de
|
input rstatus, // 2=hl-de
|
|
|
output reg [2:0]RAMSEL
|
output reg [2:0]RAMSEL
|
);
|
);
|
| Line 1243... |
Line 1243... |
default: RAMSEL = 3'b100; // I-R, tmp SP, zero, temp
|
default: RAMSEL = 3'b100; // I-R, tmp SP, zero, temp
|
endcase
|
endcase
|
end
|
end
|
endmodule
|
endmodule
|
|
|
module RAM16X8D_regs(
|
module N8080_RAM16X8D_regs(
|
input [2:0]A, // R/W address
|
input [2:0]A, // R/W address
|
input [7:0]D, // Write data input
|
input [7:0]D, // Write data input
|
input [2:0]DPRA, // Read-only address
|
input [2:0]DPRA, // Read-only address
|
input WCLK, // Write clock
|
input WCLK, // Write clock
|
input WE, // Write enable
|
input WE, // Write enable
|
