| Line 1144... |
Line 1144... |
2'b00: begin // LD I/R A
|
2'b00: begin // LD I/R A
|
ALU160_SEL = 1; // pc
|
ALU160_SEL = 1; // pc
|
DINW_SEL = 1'b0; // ALU8OUT
|
DINW_SEL = 1'b0; // ALU8OUT
|
WE = {4'b010x, !FETCH[3], FETCH[3]}; // PC, hi/lo
|
WE = {4'b010x, !FETCH[3], FETCH[3]}; // PC, hi/lo
|
ALU8OP = 29; // pass D1
|
ALU8OP = 29; // pass D1
|
REG_WSEL = 4'b100x; // IR
|
REG_WSEL = 4'b1001; // IR, write r
|
REG_RSEL = 4'b0110; // A
|
REG_RSEL = 4'b0110; // A
|
end
|
end
|
2'b01: begin // LD A I/R
|
2'b01: begin // LD A I/R
|
ALU160_SEL = 1; // pc
|
ALU160_SEL = 1; // pc
|
DINW_SEL = 1'b0; // ALU8OUT
|
DINW_SEL = 1'b0; // ALU8OUT
|
| Line 1402... |
Line 1402... |
ALU160_SEL = 0; // regs
|
ALU160_SEL = 0; // regs
|
DINW_SEL = 0; // ALU8OUT
|
DINW_SEL = 0; // ALU8OUT
|
WE = 6'bx1xx11; // PC, hi, lo
|
WE = 6'bx1xx11; // PC, hi, lo
|
ALU8OP = 29; // pass D1
|
ALU8OP = 29; // pass D1
|
ALU16OP = 4; // NOP
|
ALU16OP = 4; // NOP
|
REG_WSEL = 4'b010x; // IR
|
REG_WSEL = 4'b1001; // IR, write r
|
REG_RSEL = 4'b110x; // const
|
REG_RSEL = 4'b110x; // const
|
M1 = 0;
|
M1 = 0;
|
MREQ = 0;
|
MREQ = 0;
|
status[11:6] = 6'b110000; // IM0, DI
|
status[11:6] = 6'b110000; // IM0, DI
|
end
|
end
|
| Line 1456... |
Line 1456... |
ALU160_SEL = 1; // pc
|
ALU160_SEL = 1; // pc
|
DINW_SEL = 1; // DI
|
DINW_SEL = 1; // DI
|
WE = 6'b010x01; // PC, lo
|
WE = 6'b010x01; // PC, lo
|
ALU16OP = intop; // DEC/DEC2 (if block instruction interrupted)
|
ALU16OP = intop; // DEC/DEC2 (if block instruction interrupted)
|
next_stage = 1;
|
next_stage = 1;
|
REG_WSEL = 4'b100x; // Itmp
|
REG_WSEL = 4'b1000; // Itmp, no write r
|
MREQ = 0;
|
MREQ = 0;
|
IORQ = 1;
|
IORQ = 1;
|
status[11] = 1'b1;
|
status[11] = 1'b1;
|
status[7:6] = 2'b0; // reset IFF1, IFF2
|
status[7:6] = 2'b0; // reset IFF1, IFF2
|
end
|
end
|
