//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : ext_frame_RAM1_wrapper.v
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// File : ext_frame_RAM1_wrapper.v
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// Generated : Nov 28,2005
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// Generated : Nov 28,2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Controller for ext_frame_RAM
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// Controller for ext_frame_RAM
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// Rread as ref_frame_RAM before Inter Prediction
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// Rread as ref_frame_RAM before Inter Prediction
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// Write as dis_frame_RAM after Deblocking Filter
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// Write as dis_frame_RAM after Deblocking Filter
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module ext_RAM_ctrl (clk,reset_n,end_of_one_frame,ref_frame_RAM_rd,ref_frame_RAM_rd_addr,dis_frame_RAM_wr,
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module ext_RAM_ctrl (clk,reset_n,end_of_one_frame,ref_frame_RAM_rd,ref_frame_RAM_rd_addr,dis_frame_RAM_wr,
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dis_frame_RAM_wr_addr,ref_frame_RAM_dout,
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dis_frame_RAM_wr_addr,ref_frame_RAM_dout,
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ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
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ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data,
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ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data);
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ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data);
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input clk,reset_n;
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input clk,reset_n;
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input end_of_one_frame;
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input end_of_one_frame;
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input ref_frame_RAM_rd;
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input ref_frame_RAM_rd;
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input [13:0] ref_frame_RAM_rd_addr;
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input [13:0] ref_frame_RAM_rd_addr;
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input dis_frame_RAM_wr;
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input dis_frame_RAM_wr;
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input [13:0] dis_frame_RAM_wr_addr;
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input [13:0] dis_frame_RAM_wr_addr;
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//input [31:0] dis_frame_RAM_din;
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//input [31:0] dis_frame_RAM_din;
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input [31:0] ext_frame_RAM0_data;
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input [31:0] ext_frame_RAM0_data;
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input [31:0] ext_frame_RAM1_data;
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input [31:0] ext_frame_RAM1_data;
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output [31:0] ref_frame_RAM_dout;
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output [31:0] ref_frame_RAM_dout;
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output ext_frame_RAM0_cs_n;
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output ext_frame_RAM0_cs_n;
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output ext_frame_RAM0_wr;
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output ext_frame_RAM0_wr;
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output [13:0] ext_frame_RAM0_addr;
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output [13:0] ext_frame_RAM0_addr;
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output ext_frame_RAM1_cs_n;
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output ext_frame_RAM1_cs_n;
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output ext_frame_RAM1_wr;
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output ext_frame_RAM1_wr;
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output [13:0] ext_frame_RAM1_addr;
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output [13:0] ext_frame_RAM1_addr;
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reg ext_frame_RAM_sel; //0:ext_frame_RAM0 as dis_frame_RAM to be written
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reg ext_frame_RAM_sel; //0:ext_frame_RAM0 as dis_frame_RAM to be written
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//0:ext_frame_RAM1 as ref_frame_RAM to be read
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//0:ext_frame_RAM1 as ref_frame_RAM to be read
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//1:ext_frame_RAM0 as ref_frame_RAM to be read
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//1:ext_frame_RAM0 as ref_frame_RAM to be read
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//1:ext_frame_RAM1 as dis_frame_RAM to be written
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//1:ext_frame_RAM1 as dis_frame_RAM to be written
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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ext_frame_RAM_sel <= 1'b0;
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ext_frame_RAM_sel <= 1'b0;
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else if (end_of_one_frame)
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else if (end_of_one_frame)
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ext_frame_RAM_sel <= ~ ext_frame_RAM_sel;
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ext_frame_RAM_sel <= ~ ext_frame_RAM_sel;
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reg [31:0] ref_frame_RAM_dout;
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reg [31:0] ref_frame_RAM_dout;
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reg ext_frame_RAM0_cs_n;
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reg ext_frame_RAM0_cs_n;
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reg ext_frame_RAM0_wr;
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reg ext_frame_RAM0_wr;
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reg [13:0] ext_frame_RAM0_addr;
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reg [13:0] ext_frame_RAM0_addr;
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reg ext_frame_RAM1_cs_n;
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reg ext_frame_RAM1_cs_n;
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reg ext_frame_RAM1_wr;
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reg ext_frame_RAM1_wr;
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reg [13:0] ext_frame_RAM1_addr;
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reg [13:0] ext_frame_RAM1_addr;
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always @ (ext_frame_RAM_sel or
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always @ (ext_frame_RAM_sel or
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ref_frame_RAM_rd or ref_frame_RAM_rd_addr or ext_frame_RAM0_data or ext_frame_RAM1_data or
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ref_frame_RAM_rd or ref_frame_RAM_rd_addr or ext_frame_RAM0_data or ext_frame_RAM1_data or
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dis_frame_RAM_wr or dis_frame_RAM_wr_addr)
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dis_frame_RAM_wr or dis_frame_RAM_wr_addr)
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case (ext_frame_RAM_sel)
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case (ext_frame_RAM_sel)
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1'b0:
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1'b0:
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begin
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begin
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//ext_frame_RAM0 as dis_frame_RAM to be written
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//ext_frame_RAM0 as dis_frame_RAM to be written
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ext_frame_RAM0_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM0_wr <= dis_frame_RAM_wr;
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ext_frame_RAM0_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM0_wr <= dis_frame_RAM_wr;
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ext_frame_RAM0_addr <= dis_frame_RAM_wr_addr;
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ext_frame_RAM0_addr <= dis_frame_RAM_wr_addr;
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//ext_frame_RAM1 as ref_frame_RAM to be read
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//ext_frame_RAM1 as ref_frame_RAM to be read
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ext_frame_RAM1_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM1_wr <= 1'b0;
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ext_frame_RAM1_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM1_wr <= 1'b0;
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ext_frame_RAM1_addr <= ref_frame_RAM_rd_addr;
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ext_frame_RAM1_addr <= ref_frame_RAM_rd_addr;
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ref_frame_RAM_dout <= ext_frame_RAM1_data;
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ref_frame_RAM_dout <= ext_frame_RAM1_data;
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end
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end
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1'b1:
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1'b1:
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begin
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begin
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//ext_frame_RAM0 as ref_frame_RAM to be read
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//ext_frame_RAM0 as ref_frame_RAM to be read
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ext_frame_RAM0_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM0_wr <= 1'b0;
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ext_frame_RAM0_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM0_wr <= 1'b0;
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ext_frame_RAM0_addr <= ref_frame_RAM_rd_addr;
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ext_frame_RAM0_addr <= ref_frame_RAM_rd_addr;
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//ext_frame_RAM1 as dis_frame_RAM to be written
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//ext_frame_RAM1 as dis_frame_RAM to be written
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ext_frame_RAM1_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM1_wr <= dis_frame_RAM_wr;
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ext_frame_RAM1_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM1_wr <= dis_frame_RAM_wr;
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ext_frame_RAM1_addr <= dis_frame_RAM_wr_addr;
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ext_frame_RAM1_addr <= dis_frame_RAM_wr_addr;
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ref_frame_RAM_dout <= ext_frame_RAM0_data;
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ref_frame_RAM_dout <= ext_frame_RAM0_data;
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end
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end
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endcase
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endcase
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//assign ext_frame_RAM0_data = (!ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz;
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//assign ext_frame_RAM0_data = (!ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz;
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//assign ext_frame_RAM1_data = ( ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz;
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//assign ext_frame_RAM1_data = ( ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz;
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endmodule
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endmodule
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