//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : Intra4x4_PredMode_decoding.v
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// File : Intra4x4_PredMode_decoding.v
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// Generated : May 31, 2005
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// Generated : May 31, 2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Decoding the prediction mode for Intra4x4
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// Decoding the prediction mode for Intra4x4
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v,
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module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v,
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MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag,
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MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag,
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rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout,
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rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout,
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Intra4x4PredMode_CurrMb,
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Intra4x4PredMode_CurrMb,
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Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr,
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Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr,
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Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din
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Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din
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);
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);
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input clk,reset_n;
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input clk,reset_n;
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input [2:0] mb_pred_state;
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input [2:0] mb_pred_state;
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input [3:0] luma4x4BlkIdx;
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input [3:0] luma4x4BlkIdx;
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input [3:0] mb_num_h,mb_num_v;
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input [3:0] mb_num_h,mb_num_v;
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input [1:0] MBTypeGen_mbAddrA;
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input [1:0] MBTypeGen_mbAddrA;
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input [21:0] MBTypeGen_mbAddrB_reg;
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input [21:0] MBTypeGen_mbAddrB_reg;
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input constrained_intra_pred_flag;
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input constrained_intra_pred_flag;
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input [2:0] rem_intra4x4_pred_mode;
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input [2:0] rem_intra4x4_pred_mode;
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input prev_intra4x4_pred_mode_flag;
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input prev_intra4x4_pred_mode_flag;
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input [15:0] Intra4x4PredMode_mbAddrB_dout;
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input [15:0] Intra4x4PredMode_mbAddrB_dout;
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//input [8:0] pic_num;
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//input [8:0] pic_num;
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output [63:0] Intra4x4PredMode_CurrMb;
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output [63:0] Intra4x4PredMode_CurrMb;
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output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
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output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
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output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
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output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
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output [15:0] Intra4x4PredMode_mbAddrB_din;
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output [15:0] Intra4x4PredMode_mbAddrB_din;
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reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
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reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
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reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
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reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
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reg [15:0] Intra4x4PredMode_mbAddrB_din;
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reg [15:0] Intra4x4PredMode_mbAddrB_din;
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wire mbAddrA_availability;
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wire mbAddrA_availability;
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wire mbAddrB_availability;
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wire mbAddrB_availability;
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wire mbAddrA;
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wire mbAddrA;
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wire mbAddrB;
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wire mbAddrB;
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wire [3:0] predIntra4x4PredMode; //prediction mode obtained at `prev_intra4x4_pred_mode_flag_s
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wire [3:0] predIntra4x4PredMode; //prediction mode obtained at `prev_intra4x4_pred_mode_flag_s
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reg dcOnlyPredictionFlag;
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reg dcOnlyPredictionFlag;
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reg [15:0] Intra4x4PredMode_mbAddrA;
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reg [15:0] Intra4x4PredMode_mbAddrA;
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reg [63:0] Intra4x4PredMode_CurrMb;
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reg [63:0] Intra4x4PredMode_CurrMb;
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reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB;
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reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB;
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reg [3:0] rem_Intra4x4PredMode; //prediction mode obtained at `rem_intra4x4_pred_mode_s
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reg [3:0] rem_Intra4x4PredMode; //prediction mode obtained at `rem_intra4x4_pred_mode_s
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reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode
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reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode
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reg [1:0] MBTypeGen_mbAddrB;
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reg [1:0] MBTypeGen_mbAddrB;
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
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case (mb_num_h)
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case (mb_num_h)
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0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
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0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
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1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
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1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
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2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
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2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
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3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
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3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
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4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
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4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
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5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
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5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
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6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
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6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
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7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
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7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
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8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
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8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
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9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
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9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
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10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
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10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
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default:MBTypeGen_mbAddrB <= 0;
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default:MBTypeGen_mbAddrB <= 0;
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endcase
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endcase
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//neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order
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//neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order
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assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2
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assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2
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|| luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1;
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|| luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1;
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assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1
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assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1
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|| luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1;
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|| luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1;
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assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8
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assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8
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|| luma4x4BlkIdx == 10)? 1'b0:1'b1; //0:left MB;1:curr MB
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|| luma4x4BlkIdx == 10)? 1'b0:1'b1; //0:left MB;1:curr MB
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assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4
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assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4
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|| luma4x4BlkIdx == 5)? 1'b0:1'b1; //0:upper MB;1:curr MB
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|| luma4x4BlkIdx == 5)? 1'b0:1'b1; //0:upper MB;1:curr MB
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//dcOnlyPredictionFlag
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//dcOnlyPredictionFlag
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always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or
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always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or
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MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag)
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MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag)
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if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
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if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
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begin
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begin
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if (mbAddrA_availability == 0)
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if (mbAddrA_availability == 0)
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dcOnlyPredictionFlag <= 1;
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dcOnlyPredictionFlag <= 1;
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else if (mbAddrB_availability == 0)
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else if (mbAddrB_availability == 0)
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dcOnlyPredictionFlag <= 1;
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dcOnlyPredictionFlag <= 1;
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else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1)
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else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1)
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dcOnlyPredictionFlag <= 1;
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dcOnlyPredictionFlag <= 1;
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else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1)
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else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1)
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dcOnlyPredictionFlag <= 1;
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dcOnlyPredictionFlag <= 1;
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else
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else
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dcOnlyPredictionFlag <= 0;
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dcOnlyPredictionFlag <= 0;
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end
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end
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else
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else
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dcOnlyPredictionFlag <= 0;
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dcOnlyPredictionFlag <= 0;
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//Intra4x4PredModeA
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//Intra4x4PredModeA
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always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA
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always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA
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or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
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or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
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if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
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if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
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begin
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begin
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if (dcOnlyPredictionFlag == 1)
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if (dcOnlyPredictionFlag == 1)
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Intra4x4PredModeA <= 2;
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Intra4x4PredModeA <= 2;
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else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4
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else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4
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Intra4x4PredModeA <= 2;
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Intra4x4PredModeA <= 2;
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else
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else
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case (luma4x4BlkIdx)
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case (luma4x4BlkIdx)
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0 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[3:0];
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0 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[3:0];
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1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0];
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1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0];
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2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4];
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2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4];
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3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8];
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3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8];
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4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4];
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4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4];
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5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16];
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5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16];
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6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12];
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6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12];
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7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24];
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7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24];
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8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8];
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8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8];
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9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32];
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9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32];
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10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12];
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10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12];
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11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40];
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11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40];
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12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36];
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12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36];
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13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48];
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13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48];
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14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44];
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14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44];
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15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56];
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15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56];
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endcase
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endcase
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end
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end
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else
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else
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Intra4x4PredModeA <= 0;
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Intra4x4PredModeA <= 0;
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//Intra4x4PredModeB
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//Intra4x4PredModeB
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always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB
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always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB
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or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
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or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
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if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
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if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
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begin
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begin
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if (dcOnlyPredictionFlag == 1)
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if (dcOnlyPredictionFlag == 1)
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Intra4x4PredModeB <= 2;
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Intra4x4PredModeB <= 2;
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else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4) //not coded in Intra4x4
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else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4) //not coded in Intra4x4
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Intra4x4PredModeB <= 2;
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Intra4x4PredModeB <= 2;
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else
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else
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case (luma4x4BlkIdx)
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case (luma4x4BlkIdx)
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0 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[15:12];
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0 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[15:12];
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1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8];
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1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8];
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2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0];
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2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0];
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3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4];
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3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4];
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4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4];
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4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4];
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5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0];
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5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0];
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6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16];
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6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16];
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7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20];
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7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20];
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8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8];
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8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8];
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9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12];
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9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12];
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10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32];
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10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32];
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11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36];
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11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36];
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12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24];
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12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24];
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13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28];
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13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28];
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14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48];
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14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48];
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15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52];
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15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52];
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endcase
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endcase
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end
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end
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else
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else
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Intra4x4PredModeB <= 0;
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Intra4x4PredModeB <= 0;
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//obtain prediction mode at prev_intra4x4_pred_mode_flag_s
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//obtain prediction mode at prev_intra4x4_pred_mode_flag_s
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assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB;
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assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 0)
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if (reset_n == 0)
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predIntra4x4PredMode_reg <= 0;
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predIntra4x4PredMode_reg <= 0;
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else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0)
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else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0)
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predIntra4x4PredMode_reg <= predIntra4x4PredMode;
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predIntra4x4PredMode_reg <= predIntra4x4PredMode;
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//obtain prediction mode at rem_intra4x4_pred_mode_s
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//obtain prediction mode at rem_intra4x4_pred_mode_s
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always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg)
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always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg)
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if (mb_pred_state == `rem_intra4x4_pred_mode_s)
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if (mb_pred_state == `rem_intra4x4_pred_mode_s)
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rem_Intra4x4PredMode <= ({1'b0,rem_intra4x4_pred_mode} < predIntra4x4PredMode_reg)?
|
rem_Intra4x4PredMode <= ({1'b0,rem_intra4x4_pred_mode} < predIntra4x4PredMode_reg)?
|
{1'b0,rem_intra4x4_pred_mode}:(rem_intra4x4_pred_mode + 1);
|
{1'b0,rem_intra4x4_pred_mode}:(rem_intra4x4_pred_mode + 1);
|
else
|
else
|
rem_Intra4x4PredMode <= 0;
|
rem_Intra4x4PredMode <= 0;
|
//-----------------------------
|
//-----------------------------
|
//Intra4x4PredMode_CurrMb write
|
//Intra4x4PredMode_CurrMb write
|
//-----------------------------
|
//-----------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
Intra4x4PredMode_CurrMb <= 0;
|
Intra4x4PredMode_CurrMb <= 0;
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
case (luma4x4BlkIdx)
|
case (luma4x4BlkIdx)
|
0 :Intra4x4PredMode_CurrMb[3:0] <= predIntra4x4PredMode;
|
0 :Intra4x4PredMode_CurrMb[3:0] <= predIntra4x4PredMode;
|
1 :Intra4x4PredMode_CurrMb[7:4] <= predIntra4x4PredMode;
|
1 :Intra4x4PredMode_CurrMb[7:4] <= predIntra4x4PredMode;
|
2 :Intra4x4PredMode_CurrMb[11:8] <= predIntra4x4PredMode;
|
2 :Intra4x4PredMode_CurrMb[11:8] <= predIntra4x4PredMode;
|
3 :Intra4x4PredMode_CurrMb[15:12] <= predIntra4x4PredMode;
|
3 :Intra4x4PredMode_CurrMb[15:12] <= predIntra4x4PredMode;
|
4 :Intra4x4PredMode_CurrMb[19:16] <= predIntra4x4PredMode;
|
4 :Intra4x4PredMode_CurrMb[19:16] <= predIntra4x4PredMode;
|
5 :Intra4x4PredMode_CurrMb[23:20] <= predIntra4x4PredMode;
|
5 :Intra4x4PredMode_CurrMb[23:20] <= predIntra4x4PredMode;
|
6 :Intra4x4PredMode_CurrMb[27:24] <= predIntra4x4PredMode;
|
6 :Intra4x4PredMode_CurrMb[27:24] <= predIntra4x4PredMode;
|
7 :Intra4x4PredMode_CurrMb[31:28] <= predIntra4x4PredMode;
|
7 :Intra4x4PredMode_CurrMb[31:28] <= predIntra4x4PredMode;
|
8 :Intra4x4PredMode_CurrMb[35:32] <= predIntra4x4PredMode;
|
8 :Intra4x4PredMode_CurrMb[35:32] <= predIntra4x4PredMode;
|
9 :Intra4x4PredMode_CurrMb[39:36] <= predIntra4x4PredMode;
|
9 :Intra4x4PredMode_CurrMb[39:36] <= predIntra4x4PredMode;
|
10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode;
|
10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode;
|
11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode;
|
11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode;
|
12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode;
|
12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode;
|
13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode;
|
13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode;
|
14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode;
|
14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode;
|
15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode;
|
15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode;
|
endcase
|
endcase
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
case (luma4x4BlkIdx)
|
case (luma4x4BlkIdx)
|
0 :Intra4x4PredMode_CurrMb[3:0] <= rem_Intra4x4PredMode;
|
0 :Intra4x4PredMode_CurrMb[3:0] <= rem_Intra4x4PredMode;
|
1 :Intra4x4PredMode_CurrMb[7:4] <= rem_Intra4x4PredMode;
|
1 :Intra4x4PredMode_CurrMb[7:4] <= rem_Intra4x4PredMode;
|
2 :Intra4x4PredMode_CurrMb[11:8] <= rem_Intra4x4PredMode;
|
2 :Intra4x4PredMode_CurrMb[11:8] <= rem_Intra4x4PredMode;
|
3 :Intra4x4PredMode_CurrMb[15:12] <= rem_Intra4x4PredMode;
|
3 :Intra4x4PredMode_CurrMb[15:12] <= rem_Intra4x4PredMode;
|
4 :Intra4x4PredMode_CurrMb[19:16] <= rem_Intra4x4PredMode;
|
4 :Intra4x4PredMode_CurrMb[19:16] <= rem_Intra4x4PredMode;
|
5 :Intra4x4PredMode_CurrMb[23:20] <= rem_Intra4x4PredMode;
|
5 :Intra4x4PredMode_CurrMb[23:20] <= rem_Intra4x4PredMode;
|
6 :Intra4x4PredMode_CurrMb[27:24] <= rem_Intra4x4PredMode;
|
6 :Intra4x4PredMode_CurrMb[27:24] <= rem_Intra4x4PredMode;
|
7 :Intra4x4PredMode_CurrMb[31:28] <= rem_Intra4x4PredMode;
|
7 :Intra4x4PredMode_CurrMb[31:28] <= rem_Intra4x4PredMode;
|
8 :Intra4x4PredMode_CurrMb[35:32] <= rem_Intra4x4PredMode;
|
8 :Intra4x4PredMode_CurrMb[35:32] <= rem_Intra4x4PredMode;
|
9 :Intra4x4PredMode_CurrMb[39:36] <= rem_Intra4x4PredMode;
|
9 :Intra4x4PredMode_CurrMb[39:36] <= rem_Intra4x4PredMode;
|
10 :Intra4x4PredMode_CurrMb[43:40] <= rem_Intra4x4PredMode;
|
10 :Intra4x4PredMode_CurrMb[43:40] <= rem_Intra4x4PredMode;
|
11 :Intra4x4PredMode_CurrMb[47:44] <= rem_Intra4x4PredMode;
|
11 :Intra4x4PredMode_CurrMb[47:44] <= rem_Intra4x4PredMode;
|
12 :Intra4x4PredMode_CurrMb[51:48] <= rem_Intra4x4PredMode;
|
12 :Intra4x4PredMode_CurrMb[51:48] <= rem_Intra4x4PredMode;
|
13 :Intra4x4PredMode_CurrMb[55:52] <= rem_Intra4x4PredMode;
|
13 :Intra4x4PredMode_CurrMb[55:52] <= rem_Intra4x4PredMode;
|
14 :Intra4x4PredMode_CurrMb[59:56] <= rem_Intra4x4PredMode;
|
14 :Intra4x4PredMode_CurrMb[59:56] <= rem_Intra4x4PredMode;
|
15 :Intra4x4PredMode_CurrMb[63:60] <= rem_Intra4x4PredMode;
|
15 :Intra4x4PredMode_CurrMb[63:60] <= rem_Intra4x4PredMode;
|
endcase
|
endcase
|
//------------------------------
|
//------------------------------
|
//Intra4x4PredMode_mbAddrA write
|
//Intra4x4PredMode_mbAddrA write
|
//------------------------------
|
//------------------------------
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
Intra4x4PredMode_mbAddrA <= 0;
|
Intra4x4PredMode_mbAddrA <= 0;
|
else if (mb_num_h != 10) //mb_num_h == 10,no need to store mbAddrA
|
else if (mb_num_h != 10) //mb_num_h == 10,no need to store mbAddrA
|
begin
|
begin
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
case (luma4x4BlkIdx)
|
case (luma4x4BlkIdx)
|
5: Intra4x4PredMode_mbAddrA[3:0] <= predIntra4x4PredMode;
|
5: Intra4x4PredMode_mbAddrA[3:0] <= predIntra4x4PredMode;
|
7: Intra4x4PredMode_mbAddrA[7:4] <= predIntra4x4PredMode;
|
7: Intra4x4PredMode_mbAddrA[7:4] <= predIntra4x4PredMode;
|
13:Intra4x4PredMode_mbAddrA[11:8] <= predIntra4x4PredMode;
|
13:Intra4x4PredMode_mbAddrA[11:8] <= predIntra4x4PredMode;
|
15:Intra4x4PredMode_mbAddrA[15:12] <= predIntra4x4PredMode;
|
15:Intra4x4PredMode_mbAddrA[15:12] <= predIntra4x4PredMode;
|
endcase
|
endcase
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
case (luma4x4BlkIdx)
|
case (luma4x4BlkIdx)
|
5: Intra4x4PredMode_mbAddrA[3:0] <= rem_Intra4x4PredMode;
|
5: Intra4x4PredMode_mbAddrA[3:0] <= rem_Intra4x4PredMode;
|
7: Intra4x4PredMode_mbAddrA[7:4] <= rem_Intra4x4PredMode;
|
7: Intra4x4PredMode_mbAddrA[7:4] <= rem_Intra4x4PredMode;
|
13:Intra4x4PredMode_mbAddrA[11:8] <= rem_Intra4x4PredMode;
|
13:Intra4x4PredMode_mbAddrA[11:8] <= rem_Intra4x4PredMode;
|
15:Intra4x4PredMode_mbAddrA[15:12] <= rem_Intra4x4PredMode;
|
15:Intra4x4PredMode_mbAddrA[15:12] <= rem_Intra4x4PredMode;
|
endcase
|
endcase
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
//Intra4x4PredMode_mbAddrB RF read & write
|
//Intra4x4PredMode_mbAddrB RF read & write
|
//----------------------------------------
|
//----------------------------------------
|
always @ (reset_n or mb_num_v or mb_num_h or luma4x4BlkIdx or mb_pred_state or prev_intra4x4_pred_mode_flag
|
always @ (reset_n or mb_num_v or mb_num_h or luma4x4BlkIdx or mb_pred_state or prev_intra4x4_pred_mode_flag
|
or Intra4x4PredMode_CurrMb or predIntra4x4PredMode or rem_Intra4x4PredMode)
|
or Intra4x4PredMode_CurrMb or predIntra4x4PredMode or rem_Intra4x4PredMode)
|
if (reset_n == 0)
|
if (reset_n == 0)
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
end
|
end
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
if (prev_intra4x4_pred_mode_flag == 1 && luma4x4BlkIdx == 15 && mb_num_v != 8)//write is conditional when mb_num_v != 8
|
if (prev_intra4x4_pred_mode_flag == 1 && luma4x4BlkIdx == 15 && mb_num_v != 8)//write is conditional when mb_num_v != 8
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],predIntra4x4PredMode};
|
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],predIntra4x4PredMode};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
end
|
end
|
end
|
end
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7...
|
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h;
|
if (luma4x4BlkIdx == 15 && mb_num_v != 8) //write is conditional when mb_num_v != 8
|
if (luma4x4BlkIdx == 15 && mb_num_v != 8) //write is conditional when mb_num_v != 8
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
Intra4x4PredMode_mbAddrB_wr_n <= 0;
|
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h;
|
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40],
|
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],rem_Intra4x4PredMode};
|
Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],rem_Intra4x4PredMode};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1;
|
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
Intra4x4PredMode_mbAddrB_din <= 0;
|
end
|
end
|
|
|
/*
|
/*
|
// synopsys translate_off
|
// synopsys translate_off
|
integer tracefile;
|
integer tracefile;
|
wire [6:0] mb_num;
|
wire [6:0] mb_num;
|
assign mb_num = mb_num_v * 11 + mb_num_h;
|
assign mb_num = mb_num_v * 11 + mb_num_h;
|
|
|
initial
|
initial
|
begin
|
begin
|
tracefile = $fopen("intra_4x4_trace.txt");
|
tracefile = $fopen("intra_4x4_trace.txt");
|
end
|
end
|
always @ (posedge clk)
|
always @ (posedge clk)
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
|
begin
|
begin
|
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
pic_num,mb_num,luma4x4BlkIdx,predIntra4x4PredMode);
|
pic_num,mb_num,luma4x4BlkIdx,predIntra4x4PredMode);
|
if (luma4x4BlkIdx == 15)
|
if (luma4x4BlkIdx == 15)
|
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
end
|
end
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
|
begin
|
begin
|
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
$fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d",
|
pic_num,mb_num,luma4x4BlkIdx,rem_Intra4x4PredMode);
|
pic_num,mb_num,luma4x4BlkIdx,rem_Intra4x4PredMode);
|
if (luma4x4BlkIdx == 15)
|
if (luma4x4BlkIdx == 15)
|
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
$fdisplay (tracefile,"--------------------------------------------------------------------");
|
end
|
end
|
// synopsys translate_on
|
// synopsys translate_on
|
*/
|
*/
|
|
|
