//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : Intra_pred_reg_ctrl.v
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// File : Intra_pred_reg_ctrl.v
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// Generated : Sep 25, 2005
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// Generated : Sep 25, 2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Prepare the appropriate registers for PE0 ~ PE3
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// Prepare the appropriate registers for PE0 ~ PE3
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module Intra_pred_reg_ctrl (reset_n,gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,
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module Intra_pred_reg_ctrl (reset_n,gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,
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gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
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gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
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mbAddrA_availability,mbAddrC_availability,blk4x4_rec_counter,blk4x4_sum_counter,
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mbAddrA_availability,mbAddrC_availability,blk4x4_rec_counter,blk4x4_sum_counter,
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blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
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mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
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Intra_mbAddrB_RAM_dout,sum_right_column_reg,
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Intra_mbAddrB_RAM_dout,sum_right_column_reg,
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blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
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main_seed,PE0_sum_out,PE3_sum_out,
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main_seed,PE0_sum_out,PE3_sum_out,
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Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3,
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Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3,
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Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
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Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
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Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
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Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
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Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
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Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
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Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
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Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
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Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3,
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Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3,
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Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
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Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
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Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
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Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
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Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
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Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
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Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
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Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
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Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,Intra_mbAddrD_window,
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Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,Intra_mbAddrD_window,
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seed);
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seed);
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input reset_n;
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input reset_n;
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input gclk_intra_mbAddrA_luma;
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input gclk_intra_mbAddrA_luma;
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input gclk_intra_mbAddrA_Cb;
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input gclk_intra_mbAddrA_Cb;
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input gclk_intra_mbAddrA_Cr;
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input gclk_intra_mbAddrA_Cr;
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input gclk_intra_mbAddrB;
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input gclk_intra_mbAddrB;
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input gclk_intra_mbAddrC_luma;
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input gclk_intra_mbAddrC_luma;
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input gclk_intra_mbAddrD;
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input gclk_intra_mbAddrD;
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input gclk_seed;
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input gclk_seed;
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input mbAddrA_availability;
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input mbAddrA_availability;
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input mbAddrC_availability;
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input mbAddrC_availability;
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input [4:0] blk4x4_rec_counter;
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input [4:0] blk4x4_rec_counter;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_intra_preload_counter;
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input [2:0] blk4x4_intra_preload_counter;
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input [3:0] blk4x4_intra_precompute_counter;
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input [3:0] blk4x4_intra_precompute_counter;
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input [2:0] blk4x4_intra_calculate_counter;
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input [2:0] blk4x4_intra_calculate_counter;
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input [3:0] mb_type_general;
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input [3:0] mb_type_general;
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input [3:0] Intra4x4_predmode;
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input [3:0] Intra4x4_predmode;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra_chroma_predmode;
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input [1:0] Intra_chroma_predmode;
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input [31:0] Intra_mbAddrB_RAM_dout;
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input [31:0] Intra_mbAddrB_RAM_dout;
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input [23:0] sum_right_column_reg;
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input [23:0] sum_right_column_reg;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
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input [15:0] main_seed;
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input [15:0] main_seed;
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input [15:0] PE0_sum_out,PE3_sum_out;
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input [15:0] PE0_sum_out,PE3_sum_out;
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output [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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output [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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output [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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output [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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output [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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output [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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output [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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output [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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output [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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output [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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output [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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output [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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output [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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output [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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output [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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output [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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output [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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output [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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output [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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output [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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output [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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output [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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output [7:0] Intra_mbAddrD_window;
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output [7:0] Intra_mbAddrD_window;
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output [15:0] seed;
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output [15:0] seed;
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reg [7:0] Intra_mbAddrA_luma_reg0, Intra_mbAddrA_luma_reg1, Intra_mbAddrA_luma_reg2, Intra_mbAddrA_luma_reg3;
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reg [7:0] Intra_mbAddrA_luma_reg0, Intra_mbAddrA_luma_reg1, Intra_mbAddrA_luma_reg2, Intra_mbAddrA_luma_reg3;
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reg [7:0] Intra_mbAddrA_luma_reg4, Intra_mbAddrA_luma_reg5, Intra_mbAddrA_luma_reg6, Intra_mbAddrA_luma_reg7;
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reg [7:0] Intra_mbAddrA_luma_reg4, Intra_mbAddrA_luma_reg5, Intra_mbAddrA_luma_reg6, Intra_mbAddrA_luma_reg7;
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reg [7:0] Intra_mbAddrA_luma_reg8, Intra_mbAddrA_luma_reg9, Intra_mbAddrA_luma_reg10,Intra_mbAddrA_luma_reg11;
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reg [7:0] Intra_mbAddrA_luma_reg8, Intra_mbAddrA_luma_reg9, Intra_mbAddrA_luma_reg10,Intra_mbAddrA_luma_reg11;
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reg [7:0] Intra_mbAddrA_luma_reg12,Intra_mbAddrA_luma_reg13,Intra_mbAddrA_luma_reg14,Intra_mbAddrA_luma_reg15;
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reg [7:0] Intra_mbAddrA_luma_reg12,Intra_mbAddrA_luma_reg13,Intra_mbAddrA_luma_reg14,Intra_mbAddrA_luma_reg15;
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reg [7:0] Intra_mbAddrA_Cb_reg0,Intra_mbAddrA_Cb_reg1,Intra_mbAddrA_Cb_reg2,Intra_mbAddrA_Cb_reg3;
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reg [7:0] Intra_mbAddrA_Cb_reg0,Intra_mbAddrA_Cb_reg1,Intra_mbAddrA_Cb_reg2,Intra_mbAddrA_Cb_reg3;
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reg [7:0] Intra_mbAddrA_Cb_reg4,Intra_mbAddrA_Cb_reg5,Intra_mbAddrA_Cb_reg6,Intra_mbAddrA_Cb_reg7;
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reg [7:0] Intra_mbAddrA_Cb_reg4,Intra_mbAddrA_Cb_reg5,Intra_mbAddrA_Cb_reg6,Intra_mbAddrA_Cb_reg7;
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reg [7:0] Intra_mbAddrA_Cr_reg0,Intra_mbAddrA_Cr_reg1,Intra_mbAddrA_Cr_reg2,Intra_mbAddrA_Cr_reg3;
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reg [7:0] Intra_mbAddrA_Cr_reg0,Intra_mbAddrA_Cr_reg1,Intra_mbAddrA_Cr_reg2,Intra_mbAddrA_Cr_reg3;
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reg [7:0] Intra_mbAddrA_Cr_reg4,Intra_mbAddrA_Cr_reg5,Intra_mbAddrA_Cr_reg6,Intra_mbAddrA_Cr_reg7;
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reg [7:0] Intra_mbAddrA_Cr_reg4,Intra_mbAddrA_Cr_reg5,Intra_mbAddrA_Cr_reg6,Intra_mbAddrA_Cr_reg7;
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reg [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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reg [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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reg [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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reg [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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reg [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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reg [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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reg [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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reg [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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reg [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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reg [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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reg [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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reg [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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reg [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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reg [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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reg [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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reg [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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reg [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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reg [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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reg [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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reg [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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reg [7:0] Intra_mbAddrC_reg0,Intra_mbAddrC_reg1,Intra_mbAddrC_reg2,Intra_mbAddrC_reg3;
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reg [7:0] Intra_mbAddrC_reg0,Intra_mbAddrC_reg1,Intra_mbAddrC_reg2,Intra_mbAddrC_reg3;
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reg [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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reg [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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reg [7:0] Intra_mbAddrD_reg0,Intra_mbAddrD_reg1,Intra_mbAddrD_reg2;
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reg [7:0] Intra_mbAddrD_reg0,Intra_mbAddrD_reg1,Intra_mbAddrD_reg2;
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reg [7:0] Intra_mbAddrD_reg3,Intra_mbAddrD_reg4;
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reg [7:0] Intra_mbAddrD_reg3,Intra_mbAddrD_reg4;
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reg [7:0] Intra_mbAddrD_LeftMB_luma_reg,Intra_mbAddrD_LeftMB_Cb_reg,Intra_mbAddrD_LeftMB_Cr_reg;
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reg [7:0] Intra_mbAddrD_LeftMB_luma_reg,Intra_mbAddrD_LeftMB_Cb_reg,Intra_mbAddrD_LeftMB_Cr_reg;
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reg [7:0] Intra_mbAddrD_window;
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reg [7:0] Intra_mbAddrD_window;
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reg [15:0] seed_0,seed_1,seed_2,seed_3;
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reg [15:0] seed_0,seed_1,seed_2,seed_3;
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reg [15:0] seed;
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reg [15:0] seed;
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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//Intra_mbAddrA_luma_reg0 ~ 15
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//Intra_mbAddrA_luma_reg0 ~ 15
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//Intra_mbAddrA_Cb_reg0 ~ 7
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//Intra_mbAddrA_Cb_reg0 ~ 7
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//Intra_mbAddrA_Cr_reg0 ~ 7
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//Intra_mbAddrA_Cr_reg0 ~ 7
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//---------------------------------------------------------------------
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//---------------------------------------------------------------------
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always @ (posedge gclk_intra_mbAddrA_luma or negedge reset_n)
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always @ (posedge gclk_intra_mbAddrA_luma or negedge reset_n)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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begin
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begin
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Intra_mbAddrA_luma_reg0 <= 0; Intra_mbAddrA_luma_reg1 <= 0; Intra_mbAddrA_luma_reg2 <= 0;
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Intra_mbAddrA_luma_reg0 <= 0; Intra_mbAddrA_luma_reg1 <= 0; Intra_mbAddrA_luma_reg2 <= 0;
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Intra_mbAddrA_luma_reg3 <= 0; Intra_mbAddrA_luma_reg4 <= 0; Intra_mbAddrA_luma_reg5 <= 0;
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Intra_mbAddrA_luma_reg3 <= 0; Intra_mbAddrA_luma_reg4 <= 0; Intra_mbAddrA_luma_reg5 <= 0;
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Intra_mbAddrA_luma_reg6 <= 0; Intra_mbAddrA_luma_reg7 <= 0; Intra_mbAddrA_luma_reg8 <= 0;
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Intra_mbAddrA_luma_reg6 <= 0; Intra_mbAddrA_luma_reg7 <= 0; Intra_mbAddrA_luma_reg8 <= 0;
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Intra_mbAddrA_luma_reg9 <= 0; Intra_mbAddrA_luma_reg10 <= 0; Intra_mbAddrA_luma_reg11 <= 0;
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Intra_mbAddrA_luma_reg9 <= 0; Intra_mbAddrA_luma_reg10 <= 0; Intra_mbAddrA_luma_reg11 <= 0;
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Intra_mbAddrA_luma_reg12 <= 0; Intra_mbAddrA_luma_reg13 <= 0; Intra_mbAddrA_luma_reg14 <= 0;
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Intra_mbAddrA_luma_reg12 <= 0; Intra_mbAddrA_luma_reg13 <= 0; Intra_mbAddrA_luma_reg14 <= 0;
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Intra_mbAddrA_luma_reg15 <= 0;
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Intra_mbAddrA_luma_reg15 <= 0;
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end
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end
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else
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else
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case (blk4x4_rec_counter)
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case (blk4x4_rec_counter)
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0,1,4,5:
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0,1,4,5:
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begin
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begin
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Intra_mbAddrA_luma_reg0 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg0 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg1 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg1 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg2 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg2 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg3 <= blk4x4_sum_PE3_out;
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Intra_mbAddrA_luma_reg3 <= blk4x4_sum_PE3_out;
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end
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end
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2,3,6,7:
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2,3,6,7:
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begin
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begin
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Intra_mbAddrA_luma_reg4 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg4 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg5 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg5 <= sum_right_column_reg[15:8];
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Intra_mbAddrA_luma_reg6 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg6 <= sum_right_column_reg[23:16];
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Intra_mbAddrA_luma_reg7 <= blk4x4_sum_PE3_out;
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Intra_mbAddrA_luma_reg7 <= blk4x4_sum_PE3_out;
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end
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end
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8,9,12,13:
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8,9,12,13:
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begin
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begin
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Intra_mbAddrA_luma_reg8 <= sum_right_column_reg[7:0];
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Intra_mbAddrA_luma_reg8 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_luma_reg9 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_luma_reg9 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_luma_reg10 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_luma_reg10 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_luma_reg11 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrA_luma_reg11 <= blk4x4_sum_PE3_out;
|
end
|
end
|
10,11,14,15:
|
10,11,14,15:
|
begin
|
begin
|
Intra_mbAddrA_luma_reg12 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_luma_reg12 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_luma_reg13 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_luma_reg13 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_luma_reg14 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_luma_reg14 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_luma_reg15 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrA_luma_reg15 <= blk4x4_sum_PE3_out;
|
end
|
end
|
endcase
|
endcase
|
|
|
always @ (posedge gclk_intra_mbAddrA_Cb or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrA_Cb or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
begin
|
begin
|
Intra_mbAddrA_Cb_reg0 <= 0; Intra_mbAddrA_Cb_reg1 <= 0; Intra_mbAddrA_Cb_reg2 <= 0;
|
Intra_mbAddrA_Cb_reg0 <= 0; Intra_mbAddrA_Cb_reg1 <= 0; Intra_mbAddrA_Cb_reg2 <= 0;
|
Intra_mbAddrA_Cb_reg3 <= 0; Intra_mbAddrA_Cb_reg4 <= 0; Intra_mbAddrA_Cb_reg5 <= 0;
|
Intra_mbAddrA_Cb_reg3 <= 0; Intra_mbAddrA_Cb_reg4 <= 0; Intra_mbAddrA_Cb_reg5 <= 0;
|
Intra_mbAddrA_Cb_reg6 <= 0; Intra_mbAddrA_Cb_reg7 <= 0;
|
Intra_mbAddrA_Cb_reg6 <= 0; Intra_mbAddrA_Cb_reg7 <= 0;
|
end
|
end
|
else if (blk4x4_rec_counter == 17)
|
else if (blk4x4_rec_counter == 17)
|
begin
|
begin
|
Intra_mbAddrA_Cb_reg0 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cb_reg0 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cb_reg1 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cb_reg1 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cb_reg2 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cb_reg2 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cb_reg3 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrA_Cb_reg3 <= blk4x4_sum_PE3_out;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrA_Cb_reg4 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cb_reg4 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cb_reg5 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cb_reg5 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cb_reg6 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cb_reg6 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cb_reg7 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrA_Cb_reg7 <= blk4x4_sum_PE3_out;
|
end
|
end
|
|
|
always @ (posedge gclk_intra_mbAddrA_Cr or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrA_Cr or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
begin
|
begin
|
Intra_mbAddrA_Cr_reg0 <= 0; Intra_mbAddrA_Cr_reg1 <= 0; Intra_mbAddrA_Cr_reg2 <= 0;
|
Intra_mbAddrA_Cr_reg0 <= 0; Intra_mbAddrA_Cr_reg1 <= 0; Intra_mbAddrA_Cr_reg2 <= 0;
|
Intra_mbAddrA_Cr_reg3 <= 0; Intra_mbAddrA_Cr_reg4 <= 0; Intra_mbAddrA_Cr_reg5 <= 0;
|
Intra_mbAddrA_Cr_reg3 <= 0; Intra_mbAddrA_Cr_reg4 <= 0; Intra_mbAddrA_Cr_reg5 <= 0;
|
Intra_mbAddrA_Cr_reg6 <= 0; Intra_mbAddrA_Cr_reg7 <= 0;
|
Intra_mbAddrA_Cr_reg6 <= 0; Intra_mbAddrA_Cr_reg7 <= 0;
|
end
|
end
|
else if (blk4x4_rec_counter == 21)
|
else if (blk4x4_rec_counter == 21)
|
begin
|
begin
|
Intra_mbAddrA_Cr_reg0 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cr_reg0 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cr_reg1 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cr_reg1 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cr_reg2 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cr_reg2 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cr_reg3 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrA_Cr_reg3 <= blk4x4_sum_PE3_out;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrA_Cr_reg4 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cr_reg4 <= sum_right_column_reg[7:0];
|
Intra_mbAddrA_Cr_reg5 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cr_reg5 <= sum_right_column_reg[15:8];
|
Intra_mbAddrA_Cr_reg6 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cr_reg6 <= sum_right_column_reg[23:16];
|
Intra_mbAddrA_Cr_reg7 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrA_Cr_reg7 <= blk4x4_sum_PE3_out;
|
end
|
end
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
//Intra_mbAddrB_reg0 ~ 15
|
//Intra_mbAddrB_reg0 ~ 15
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
always @ (posedge gclk_intra_mbAddrB or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrB or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
begin
|
begin
|
Intra_mbAddrB_reg0 <= 0; Intra_mbAddrB_reg1 <= 0; Intra_mbAddrB_reg2 <= 0;
|
Intra_mbAddrB_reg0 <= 0; Intra_mbAddrB_reg1 <= 0; Intra_mbAddrB_reg2 <= 0;
|
Intra_mbAddrB_reg3 <= 0; Intra_mbAddrB_reg4 <= 0; Intra_mbAddrB_reg5 <= 0;
|
Intra_mbAddrB_reg3 <= 0; Intra_mbAddrB_reg4 <= 0; Intra_mbAddrB_reg5 <= 0;
|
Intra_mbAddrB_reg6 <= 0; Intra_mbAddrB_reg7 <= 0; Intra_mbAddrB_reg8 <= 0;
|
Intra_mbAddrB_reg6 <= 0; Intra_mbAddrB_reg7 <= 0; Intra_mbAddrB_reg8 <= 0;
|
Intra_mbAddrB_reg9 <= 0; Intra_mbAddrB_reg10 <= 0; Intra_mbAddrB_reg11 <= 0;
|
Intra_mbAddrB_reg9 <= 0; Intra_mbAddrB_reg10 <= 0; Intra_mbAddrB_reg11 <= 0;
|
Intra_mbAddrB_reg12 <= 0; Intra_mbAddrB_reg13 <= 0; Intra_mbAddrB_reg14 <= 0;
|
Intra_mbAddrB_reg12 <= 0; Intra_mbAddrB_reg13 <= 0; Intra_mbAddrB_reg14 <= 0;
|
Intra_mbAddrB_reg15 <= 0;
|
Intra_mbAddrB_reg15 <= 0;
|
end
|
end
|
//Intra4x4
|
//Intra4x4
|
else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
begin
|
begin
|
// blk 0,1,4,5,load from RAM
|
// blk 0,1,4,5,load from RAM
|
if (blk4x4_intra_preload_counter == 3'b001)
|
if (blk4x4_intra_preload_counter == 3'b001)
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0:
|
0:
|
begin
|
begin
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
1:
|
1:
|
begin
|
begin
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
4:
|
4:
|
begin
|
begin
|
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
5:
|
5:
|
begin
|
begin
|
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
endcase
|
endcase
|
//other blocks,from blk4x4_sum output
|
//other blocks,from blk4x4_sum output
|
else if ((blk4x4_rec_counter != 10 || blk4x4_rec_counter != 11 || blk4x4_rec_counter != 14 ||
|
else if ((blk4x4_rec_counter != 10 || blk4x4_rec_counter != 11 || blk4x4_rec_counter != 14 ||
|
blk4x4_rec_counter != 15) && blk4x4_sum_counter == 3'd3)
|
blk4x4_rec_counter != 15) && blk4x4_sum_counter == 3'd3)
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,2,8:
|
0,2,8:
|
begin
|
begin
|
Intra_mbAddrB_reg0 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg0 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg1 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg1 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg2 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg2 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg3 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrB_reg3 <= blk4x4_sum_PE3_out;
|
end
|
end
|
1,3,9:
|
1,3,9:
|
begin
|
begin
|
Intra_mbAddrB_reg4 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg4 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg5 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg5 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg6 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg6 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg7 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrB_reg7 <= blk4x4_sum_PE3_out;
|
end
|
end
|
4,6,12:
|
4,6,12:
|
begin
|
begin
|
Intra_mbAddrB_reg8 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg8 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg9 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg9 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg10 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg10 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg11 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrB_reg11 <= blk4x4_sum_PE3_out;
|
end
|
end
|
5,7,13:
|
5,7,13:
|
begin
|
begin
|
Intra_mbAddrB_reg12 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg12 <= blk4x4_sum_PE0_out;
|
Intra_mbAddrB_reg13 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg13 <= blk4x4_sum_PE1_out;
|
Intra_mbAddrB_reg14 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg14 <= blk4x4_sum_PE2_out;
|
Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out;
|
Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
//Intra16x16
|
//Intra16x16
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
case (blk4x4_intra_preload_counter)
|
case (blk4x4_intra_preload_counter)
|
3'b100:
|
3'b100:
|
begin
|
begin
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
3'b011:
|
3'b011:
|
begin
|
begin
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
3'b010:
|
3'b010:
|
begin
|
begin
|
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
3'b001:
|
3'b001:
|
begin
|
begin
|
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
endcase
|
endcase
|
//Chroma
|
//Chroma
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
begin
|
begin
|
if (blk4x4_intra_preload_counter == 3'b010)
|
if (blk4x4_intra_preload_counter == 3'b010)
|
begin
|
begin
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
else if (blk4x4_intra_preload_counter == 3'b001)
|
else if (blk4x4_intra_preload_counter == 3'b001)
|
begin
|
begin
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
end
|
end
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
//Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with
|
//Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with
|
// blkIdx = 0/1/4/5
|
// blkIdx = 0/1/4/5
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
|
|
always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
begin
|
begin
|
Intra_mbAddrC_reg0 <= 0; Intra_mbAddrC_reg1 <= 0;
|
Intra_mbAddrC_reg0 <= 0; Intra_mbAddrC_reg1 <= 0;
|
Intra_mbAddrC_reg2 <= 0; Intra_mbAddrC_reg3 <= 0;
|
Intra_mbAddrC_reg2 <= 0; Intra_mbAddrC_reg3 <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrC_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrC_reg0 <= Intra_mbAddrB_RAM_dout[7:0];
|
Intra_mbAddrC_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrC_reg1 <= Intra_mbAddrB_RAM_dout[15:8];
|
Intra_mbAddrC_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrC_reg2 <= Intra_mbAddrB_RAM_dout[23:16];
|
Intra_mbAddrC_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrC_reg3 <= Intra_mbAddrB_RAM_dout[31:24];
|
end
|
end
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
//Intra_mbAddrD_reg0 ~ 5
|
//Intra_mbAddrD_reg0 ~ 5
|
//Intra_mbAddrD_LeftMB_reg
|
//Intra_mbAddrD_LeftMB_reg
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
Intra_mbAddrD_LeftMB_luma_reg <= 0;
|
Intra_mbAddrD_LeftMB_luma_reg <= 0;
|
else if (blk4x4_rec_counter == 15)
|
else if (blk4x4_rec_counter == 15)
|
Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3) //Intra4x4
|
else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3) //Intra4x4
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3;
|
0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3;
|
2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7;
|
2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7;
|
8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11;
|
8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11;
|
endcase
|
endcase
|
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
Intra_mbAddrD_LeftMB_Cb_reg <= 0;
|
Intra_mbAddrD_LeftMB_Cb_reg <= 0;
|
else if (blk4x4_rec_counter == 19)
|
else if (blk4x4_rec_counter == 19)
|
Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
Intra_mbAddrD_LeftMB_Cr_reg <= 0;
|
Intra_mbAddrD_LeftMB_Cr_reg <= 0;
|
else if (blk4x4_rec_counter == 23)
|
else if (blk4x4_rec_counter == 23)
|
Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24];
|
|
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
always @ (posedge gclk_intra_mbAddrD or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
begin
|
begin
|
Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0;
|
Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0;
|
Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0;
|
Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0;
|
end
|
end
|
else if (mb_type_general[3:2] == 2'b11)
|
else if (mb_type_general[3:2] == 2'b11)
|
begin
|
begin
|
//load from Intra_mbAddrB_RAM for blk 1/4/5
|
//load from Intra_mbAddrB_RAM for blk 1/4/5
|
if (blk4x4_intra_preload_counter == 3'b010)
|
if (blk4x4_intra_preload_counter == 3'b010)
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24];
|
1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24];
|
4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24];
|
4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24];
|
5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24];
|
5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24];
|
endcase
|
endcase
|
//update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4
|
//update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4
|
//After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7
|
//After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7
|
//After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13
|
//After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13
|
//After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15
|
//After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15
|
else
|
else
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out;
|
0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out;
|
1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out;
|
1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out;
|
2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out;
|
2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out;
|
3 :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out;
|
3 :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out;
|
4,9 :Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out;
|
4,9 :Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out;
|
endcase
|
endcase
|
end
|
end
|
//---------------------------
|
//---------------------------
|
//sliding window output
|
//sliding window output
|
//---------------------------
|
//---------------------------
|
//Intra_mbAddrA_reg0 ~ 15
|
//Intra_mbAddrA_reg0 ~ 15
|
always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or
|
always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or
|
blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode
|
blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode
|
or mbAddrA_availability
|
or mbAddrA_availability
|
|
|
or Intra_mbAddrA_luma_reg0 or Intra_mbAddrA_luma_reg1 or Intra_mbAddrA_luma_reg2
|
or Intra_mbAddrA_luma_reg0 or Intra_mbAddrA_luma_reg1 or Intra_mbAddrA_luma_reg2
|
or Intra_mbAddrA_luma_reg3 or Intra_mbAddrA_luma_reg4 or Intra_mbAddrA_luma_reg5
|
or Intra_mbAddrA_luma_reg3 or Intra_mbAddrA_luma_reg4 or Intra_mbAddrA_luma_reg5
|
or Intra_mbAddrA_luma_reg6 or Intra_mbAddrA_luma_reg7 or Intra_mbAddrA_luma_reg8
|
or Intra_mbAddrA_luma_reg6 or Intra_mbAddrA_luma_reg7 or Intra_mbAddrA_luma_reg8
|
or Intra_mbAddrA_luma_reg9 or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11
|
or Intra_mbAddrA_luma_reg9 or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11
|
or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14
|
or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14
|
or Intra_mbAddrA_luma_reg15
|
or Intra_mbAddrA_luma_reg15
|
|
|
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2
|
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2
|
or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5
|
or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5
|
or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
|
|
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2
|
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2
|
or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5
|
or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5
|
or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
if (mb_type_general[3] == 1'b1)
|
if (mb_type_general[3] == 1'b1)
|
begin
|
begin
|
//Intra4x4
|
//Intra4x4
|
//Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane
|
//Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane
|
if (blk4x4_rec_counter < 16 &&
|
if (blk4x4_rec_counter < 16 &&
|
(mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && (
|
(mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && (
|
(Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
(Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
(Intra16x16_predmode == `Intra16x16_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
(Intra16x16_predmode == `Intra16x16_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
(Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_precompute_counter != 0)))))
|
(Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_precompute_counter != 0)))))
|
begin
|
begin
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_luma_reg0;
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_luma_reg0;
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_luma_reg1;
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_luma_reg1;
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_luma_reg2;
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_luma_reg2;
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_luma_reg3;
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_luma_reg3;
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_luma_reg4;
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_luma_reg4;
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_luma_reg5;
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_luma_reg5;
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_luma_reg6;
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_luma_reg6;
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_luma_reg7;
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_luma_reg7;
|
Intra_mbAddrA_reg8 <= Intra_mbAddrA_luma_reg8;
|
Intra_mbAddrA_reg8 <= Intra_mbAddrA_luma_reg8;
|
Intra_mbAddrA_reg9 <= Intra_mbAddrA_luma_reg9;
|
Intra_mbAddrA_reg9 <= Intra_mbAddrA_luma_reg9;
|
Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10;
|
Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10;
|
Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11;
|
Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11;
|
Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12;
|
Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12;
|
Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13;
|
Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13;
|
Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14;
|
Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14;
|
Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15;
|
Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15;
|
end
|
end
|
//Chroma Cb
|
//Chroma Cb
|
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && (
|
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && (
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
begin
|
begin
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cb_reg0;
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cb_reg0;
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cb_reg1;
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cb_reg1;
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cb_reg2;
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cb_reg2;
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cb_reg3;
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cb_reg3;
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cb_reg4;
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cb_reg4;
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cb_reg5;
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cb_reg5;
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cb_reg6;
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cb_reg6;
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cb_reg7;
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cb_reg7;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
end
|
end
|
//Chroma Cr
|
//Chroma Cr
|
else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && (
|
else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && (
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) ||
|
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
(Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) ||
|
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
(Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0)))
|
begin
|
begin
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cr_reg0;
|
Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cr_reg0;
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cr_reg1;
|
Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cr_reg1;
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cr_reg2;
|
Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cr_reg2;
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cr_reg3;
|
Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cr_reg3;
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cr_reg4;
|
Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cr_reg4;
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cr_reg5;
|
Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cr_reg5;
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cr_reg6;
|
Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cr_reg6;
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cr_reg7;
|
Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cr_reg7;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0;
|
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0;
|
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0;
|
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0;
|
end
|
end
|
//Intra_mbAddrA_window0 ~ 3
|
//Intra_mbAddrA_window0 ~ 3
|
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability
|
|
|
or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
|
or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
|
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
|
|
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3
|
or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3
|
or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7
|
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3
|
or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3
|
or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7)
|
if (mb_type_general[3] == 1'b1)
|
if (mb_type_general[3] == 1'b1)
|
begin
|
begin
|
//Intra4x4 && Intra16x16_horizontal
|
//Intra4x4 && Intra16x16_horizontal
|
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
(mb_type_general[2] == 1'b1 || (
|
(mb_type_general[2] == 1'b1 || (
|
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal))))
|
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal))))
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,1,4,5:
|
0,1,4,5:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3;
|
end
|
end
|
2,3,6,7:
|
2,3,6,7:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7;
|
end
|
end
|
8,9,12,13:
|
8,9,12,13:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11;
|
end
|
end
|
10,11,14,15:
|
10,11,14,15:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
end
|
end
|
endcase
|
endcase
|
//Chroma Cb/Cr Horizontal & DC
|
//Chroma Cb/Cr Horizontal & DC
|
else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 &&
|
else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 &&
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability)))
|
(Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability)))
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
16,17:
|
16,17:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3;
|
end
|
end
|
18,19:
|
18,19:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7;
|
end
|
end
|
20,21:
|
20,21:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3;
|
end
|
end
|
22,23:
|
22,23:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4;
|
Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5;
|
Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6;
|
Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7;
|
Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0;
|
end
|
end
|
|
|
|
|
//Intra_mbAddrB_window0 ~ 3
|
//Intra_mbAddrB_window0 ~ 3
|
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter
|
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2
|
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2
|
or Intra_mbAddrB_reg3 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5
|
or Intra_mbAddrB_reg3 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5
|
or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8
|
or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8
|
or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14
|
or Intra_mbAddrB_reg15)
|
or Intra_mbAddrB_reg15)
|
if (mb_type_general[3] == 1'b1)
|
if (mb_type_general[3] == 1'b1)
|
begin
|
begin
|
//Intra4x4 && Intra16x16_Vertical
|
//Intra4x4 && Intra16x16_Vertical
|
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 &&
|
(mb_type_general[2] == 1'b1 || (
|
(mb_type_general[2] == 1'b1 || (
|
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical))))
|
(mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical))))
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,2,8,10:
|
0,2,8,10:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
end
|
end
|
1,3,9,11:
|
1,3,9,11:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
end
|
end
|
4,6,12,14:
|
4,6,12,14:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8;
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11;
|
end
|
end
|
5,7,13,15:
|
5,7,13,15:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12;
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
end
|
end
|
endcase
|
endcase
|
//Chroma Cb/Cr Vertical and DC
|
//Chroma Cb/Cr Vertical and DC
|
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 &&
|
else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 &&
|
(Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0)
|
(Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0)
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
16,18,20,22:
|
16,18,20,22:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3;
|
end
|
end
|
17,19,21,23:
|
17,19,21,23:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
end
|
end
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0;
|
end
|
end
|
//Intra_mbAddrC_window0 ~ 3
|
//Intra_mbAddrC_window0 ~ 3
|
always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode
|
always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode
|
or Intra_mbAddrC_reg0 or Intra_mbAddrC_reg1 or Intra_mbAddrC_reg2 or Intra_mbAddrC_reg3
|
or Intra_mbAddrC_reg0 or Intra_mbAddrC_reg1 or Intra_mbAddrC_reg2 or Intra_mbAddrC_reg3
|
or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7
|
or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7
|
or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
or mbAddrC_availability or Intra_mbAddrB_window3)
|
or mbAddrC_availability or Intra_mbAddrB_window3)
|
if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && (
|
if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && (
|
Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16)
|
Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16)
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,1,4:
|
0,1,4:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0;
|
Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0;
|
Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1;
|
Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1;
|
Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2;
|
Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2;
|
Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3;
|
Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3;
|
end
|
end
|
5:
|
5:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15;
|
end
|
end
|
2,8,10:
|
2,8,10:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg4;
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg4;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg5;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg5;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg6;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg6;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg7;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg7;
|
end
|
end
|
9:
|
9:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg8;
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg8;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg9;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg9;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg10;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg10;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg11;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg11;
|
end
|
end
|
6,12,14:
|
6,12,14:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg12;
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_reg12;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg13;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_reg13;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg14;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_reg14;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg15;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_reg15;
|
end
|
end
|
3,11,7,13,15:
|
3,11,7,13,15:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window0 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window1 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window2 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_window3;
|
Intra_mbAddrC_window3 <= Intra_mbAddrB_window3;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
end
|
end
|
endcase
|
endcase
|
else
|
else
|
begin
|
begin
|
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0;
|
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0;
|
end
|
end
|
|
|
//Intra_mbAddrD_window
|
//Intra_mbAddrD_window
|
always @ (mb_type_general[3:2] or blk4x4_rec_counter
|
always @ (mb_type_general[3:2] or blk4x4_rec_counter
|
or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter
|
or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter
|
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2
|
or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2
|
or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4
|
or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4
|
or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg)
|
or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg)
|
//Intra
|
//Intra
|
if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0))
|
if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0))
|
begin
|
begin
|
//Intra luma
|
//Intra luma
|
if (blk4x4_rec_counter[4] == 1'b0)
|
if (blk4x4_rec_counter[4] == 1'b0)
|
begin
|
begin
|
//Intra4x4 luma
|
//Intra4x4 luma
|
if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right ||
|
if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right ||
|
Intra4x4_predmode == `Intra4x4_Vertical_Right ||
|
Intra4x4_predmode == `Intra4x4_Vertical_Right ||
|
Intra4x4_predmode == `Intra4x4_Horizontal_Down))
|
Intra4x4_predmode == `Intra4x4_Horizontal_Down))
|
case (blk4x4_rec_counter[3:0])
|
case (blk4x4_rec_counter[3:0])
|
0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg;
|
0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg;
|
3,5,13 :Intra_mbAddrD_window <= Intra_mbAddrD_reg0;
|
3,5,13 :Intra_mbAddrD_window <= Intra_mbAddrD_reg0;
|
1,6,11 :Intra_mbAddrD_window <= Intra_mbAddrD_reg1;
|
1,6,11 :Intra_mbAddrD_window <= Intra_mbAddrD_reg1;
|
9,15 :Intra_mbAddrD_window <= Intra_mbAddrD_reg2;
|
9,15 :Intra_mbAddrD_window <= Intra_mbAddrD_reg2;
|
12 :Intra_mbAddrD_window <= Intra_mbAddrD_reg3;
|
12 :Intra_mbAddrD_window <= Intra_mbAddrD_reg3;
|
4,7,14 :Intra_mbAddrD_window <= Intra_mbAddrD_reg4;
|
4,7,14 :Intra_mbAddrD_window <= Intra_mbAddrD_reg4;
|
endcase
|
endcase
|
//Intra16x16
|
//Intra16x16
|
else
|
else
|
Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0;
|
Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0;
|
end
|
end
|
//Intra chroma
|
//Intra chroma
|
else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane)
|
else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane)
|
Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg;
|
Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg;
|
else
|
else
|
Intra_mbAddrD_window <= 0;
|
Intra_mbAddrD_window <= 0;
|
end
|
end
|
//Inter
|
//Inter
|
else
|
else
|
Intra_mbAddrD_window <= 0;
|
Intra_mbAddrD_window <= 0;
|
|
|
//seed
|
//seed
|
always @ (posedge gclk_seed or negedge reset_n)
|
always @ (posedge gclk_seed or negedge reset_n)
|
if (reset_n == 1'b0)
|
if (reset_n == 1'b0)
|
begin
|
begin
|
seed_0 <= 0; seed_1 <= 0; seed_2 <= 0;
|
seed_0 <= 0; seed_1 <= 0; seed_2 <= 0;
|
end
|
end
|
else if (blk4x4_intra_precompute_counter == 1)
|
else if (blk4x4_intra_precompute_counter == 1)
|
seed_0 <= main_seed;
|
seed_0 <= main_seed;
|
else
|
else
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,2,8,16,20 :seed_0 <= PE3_sum_out;
|
0,2,8,16,20 :seed_0 <= PE3_sum_out;
|
1,9 :seed_1 <= PE0_sum_out;
|
1,9 :seed_1 <= PE0_sum_out;
|
3,11 :seed_2 <= PE0_sum_out;
|
3,11 :seed_2 <= PE0_sum_out;
|
endcase
|
endcase
|
|
|
always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode
|
always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2)
|
or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2)
|
if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16)
|
if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16)
|
case (blk4x4_rec_counter)
|
case (blk4x4_rec_counter)
|
0,2,8,10:seed <= seed_0;
|
0,2,8,10:seed <= seed_0;
|
4,12 :seed <= seed_1;
|
4,12 :seed <= seed_1;
|
6,14 :seed <= seed_2;
|
6,14 :seed <= seed_2;
|
default :seed <= 0;
|
default :seed <= 0;
|
endcase
|
endcase
|
else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15)
|
else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15)
|
if (blk4x4_rec_counter[0] == 1'b0) //16,18,20,22
|
if (blk4x4_rec_counter[0] == 1'b0) //16,18,20,22
|
seed <= seed_0;
|
seed <= seed_0;
|
else
|
else
|
seed <= 0;
|
seed <= 0;
|
else
|
else
|
seed <= 0;
|
seed <= 0;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
