//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : hybrid_pipeline_ctrl.v
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// File : hybrid_pipeline_ctrl.v
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// Generated : Sept 5, 2005
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// Generated : Sept 5, 2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Control 4x4 block level pipeline for reconstruction
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// Control 4x4 block level pipeline for reconstruction
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// Receive the 1cycle end_of_xxx signal(combinational)
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// Receive the 1cycle end_of_xxx signal(combinational)
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// Generated the 1cycle trigger_xxx signal
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// Generated the 1cycle trigger_xxx signal
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Revise log
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// Revise log
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// 1.April 11,2006
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// 1.April 11,2006
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// Modify the 1cycle trigger_xxx signal from registers to combinational logic to save decoding clock cycles
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// Modify the 1cycle trigger_xxx signal from registers to combinational logic to save decoding clock cycles
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module hybrid_pipeline_ctrl (clk,reset_n,mb_num_h,mb_num_v,blk4x4_rec_counter,CodedBlockPatternLuma,CodedBlockPatternChroma,
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module hybrid_pipeline_ctrl (clk,reset_n,mb_num_h,mb_num_v,blk4x4_rec_counter,CodedBlockPatternLuma,CodedBlockPatternChroma,
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mb_type_general,slice_data_state,residual_state,TotalCoeff,Is_skip_run_entry,skip_mv_calc,
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mb_type_general,slice_data_state,residual_state,TotalCoeff,Is_skip_run_entry,skip_mv_calc,
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end_of_one_residual_block,end_of_DCBlk_IQIT,end_of_ACBlk4x4_IQIT,end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,
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end_of_one_residual_block,end_of_DCBlk_IQIT,end_of_ACBlk4x4_IQIT,end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,
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end_of_one_blk4x4_sum,end_of_MB_DF,disable_DF,
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end_of_one_blk4x4_sum,end_of_MB_DF,disable_DF,
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curr_CBPLuma_IsZero,end_of_MB_DEC,trigger_CAVLC,trigger_blk4x4_intra_pred,
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curr_CBPLuma_IsZero,end_of_MB_DEC,trigger_CAVLC,trigger_blk4x4_intra_pred,
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trigger_blk4x4_inter_pred,trigger_blk4x4_rec_sum);
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trigger_blk4x4_inter_pred,trigger_blk4x4_rec_sum);
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input clk,reset_n;
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input clk,reset_n;
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input [3:0] mb_num_h;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input [3:0] mb_num_v;
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input [4:0] blk4x4_rec_counter;
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input [4:0] blk4x4_rec_counter;
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input [3:0] CodedBlockPatternLuma;
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input [3:0] CodedBlockPatternLuma;
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input [1:0] CodedBlockPatternChroma;
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input [1:0] CodedBlockPatternChroma;
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input [3:0] mb_type_general;
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input [3:0] mb_type_general;
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input [3:0] slice_data_state;
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input [3:0] slice_data_state;
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input [3:0] residual_state;
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input [3:0] residual_state;
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input [4:0] TotalCoeff;
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input [4:0] TotalCoeff;
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input Is_skip_run_entry;
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input Is_skip_run_entry;
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input skip_mv_calc;
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input skip_mv_calc;
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input end_of_one_residual_block;
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input end_of_one_residual_block;
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input end_of_DCBlk_IQIT;
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input end_of_DCBlk_IQIT;
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input end_of_ACBlk4x4_IQIT;
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input end_of_ACBlk4x4_IQIT;
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input end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,end_of_one_blk4x4_sum;
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input end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,end_of_one_blk4x4_sum;
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input end_of_MB_DF;
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input end_of_MB_DF;
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input disable_DF;
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input disable_DF;
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output curr_CBPLuma_IsZero;
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output curr_CBPLuma_IsZero;
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output end_of_MB_DEC;
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output end_of_MB_DEC;
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output trigger_CAVLC;
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output trigger_CAVLC;
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output trigger_blk4x4_intra_pred,trigger_blk4x4_inter_pred;
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output trigger_blk4x4_intra_pred,trigger_blk4x4_inter_pred;
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output trigger_blk4x4_rec_sum;
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output trigger_blk4x4_rec_sum;
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//change trigger_blk4x4_intra_pred from combination to reg
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//change trigger_blk4x4_intra_pred from combination to reg
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reg trigger_CAVLC; //combination
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reg trigger_CAVLC; //combination
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reg trigger_blk4x4_intra_pred; //reg
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reg trigger_blk4x4_intra_pred; //reg
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reg trigger_blk4x4_inter_pred; //reg
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reg trigger_blk4x4_inter_pred; //reg
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reg trigger_blk4x4_rec_sum; //combination
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reg trigger_blk4x4_rec_sum; //combination
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//CBPLuma only make sense for residual_state == LumaLevel_s
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//CBPLuma only make sense for residual_state == LumaLevel_s
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//CBPLuma is derived to help judge whether res_blk4x4_IsAllZero caused by CodedBlockPattern != 4'b1111
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//CBPLuma is derived to help judge whether res_blk4x4_IsAllZero caused by CodedBlockPattern != 4'b1111
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reg curr_CBPLuma_IsZero;
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reg curr_CBPLuma_IsZero;
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always @ (blk4x4_rec_counter or CodedBlockPatternLuma)
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always @ (blk4x4_rec_counter or CodedBlockPatternLuma)
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if (blk4x4_rec_counter < 16)
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if (blk4x4_rec_counter < 16)
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case (blk4x4_rec_counter[3:2])
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case (blk4x4_rec_counter[3:2])
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2'b00:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[0];
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2'b00:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[0];
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2'b01:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[1];
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2'b01:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[1];
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2'b10:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[2];
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2'b10:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[2];
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2'b11:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[3];
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2'b11:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[3];
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endcase
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endcase
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else
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else
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curr_CBPLuma_IsZero <= 0;
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curr_CBPLuma_IsZero <= 0;
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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//signals to trigger:
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//signals to trigger:
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// 1.4x4 blk CAVLC
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// 1.4x4 blk CAVLC
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// 2.4x4 Intra Prediction
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// 2.4x4 Intra Prediction
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// 3.4x4 Inter Prediction
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// 3.4x4 Inter Prediction
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// 4.4x4 reconstruction sum
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// 4.4x4 reconstruction sum
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// 5.16x16 deblocking filter
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// 5.16x16 deblocking filter
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// All the trigger_xxx signals are generated by sequential logic
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// All the trigger_xxx signals are generated by sequential logic
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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//1. trigger_CAVLC: when reconstruction is dealing with skip_run or zero residual (construction
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//1. trigger_CAVLC: when reconstruction is dealing with skip_run or zero residual (construction
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// only from inter/intra prediction) blocks,CAVLC decoder,as well as whole bitstream parsing FSM,
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// only from inter/intra prediction) blocks,CAVLC decoder,as well as whole bitstream parsing FSM,
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// needs to be stalled and wait until the reconstruction process of previous
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// needs to be stalled and wait until the reconstruction process of previous
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always @ (slice_data_state or residual_state or mb_type_general[3:2] or CodedBlockPatternLuma
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always @ (slice_data_state or residual_state or mb_type_general[3:2] or CodedBlockPatternLuma
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or CodedBlockPatternChroma or end_of_one_residual_block or end_of_DCBlk_IQIT or end_of_one_blk4x4_sum
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or CodedBlockPatternChroma or end_of_one_residual_block or end_of_DCBlk_IQIT or end_of_one_blk4x4_sum
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or blk4x4_rec_counter or TotalCoeff or curr_CBPLuma_IsZero)
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or blk4x4_rec_counter or TotalCoeff or curr_CBPLuma_IsZero)
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// Entry
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// Entry
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if (slice_data_state == `residual && residual_state == `rst_residual)
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if (slice_data_state == `residual && residual_state == `rst_residual)
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begin
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begin
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if (mb_type_general[3:2] == 2'b10) //Intra16x16:first block must be DC
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if (mb_type_general[3:2] == 2'b10) //Intra16x16:first block must be DC
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trigger_CAVLC <= 1'b1;
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trigger_CAVLC <= 1'b1;
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else if (CodedBlockPatternLuma[0] == 1'b0) //First 8x8 block has no residuals
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else if (CodedBlockPatternLuma[0] == 1'b0) //First 8x8 block has no residuals
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trigger_CAVLC <= 1'b0;
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trigger_CAVLC <= 1'b0;
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else //normal case
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else //normal case
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trigger_CAVLC <= 1'b1;
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trigger_CAVLC <= 1'b1;
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end
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end
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// End of one DC
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// End of one DC
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else if ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
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else if ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
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residual_state == `ChromaDCLevel_Cr_s) && ((end_of_one_residual_block && TotalCoeff == 0)|| end_of_DCBlk_IQIT))
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residual_state == `ChromaDCLevel_Cr_s) && ((end_of_one_residual_block && TotalCoeff == 0)|| end_of_DCBlk_IQIT))
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case (residual_state)
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case (residual_state)
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`Intra16x16DCLevel_s: //end of luma DC
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`Intra16x16DCLevel_s: //end of luma DC
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trigger_CAVLC <= (CodedBlockPatternLuma[0] == 1'b0)? 1'b0:1'b1;
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trigger_CAVLC <= (CodedBlockPatternLuma[0] == 1'b0)? 1'b0:1'b1;
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`ChromaDCLevel_Cb_s: //end of chroma DC Cb,trigger chroma DC Cr now!
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`ChromaDCLevel_Cb_s: //end of chroma DC Cb,trigger chroma DC Cr now!
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trigger_CAVLC <= 1'b1;
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trigger_CAVLC <= 1'b1;
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`ChromaDCLevel_Cr_s: //end of chroma DC Cr
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`ChromaDCLevel_Cr_s: //end of chroma DC Cr
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trigger_CAVLC <= (CodedBlockPatternChroma == 2'b01)? 1'b0:1'b1;
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trigger_CAVLC <= (CodedBlockPatternChroma == 2'b01)? 1'b0:1'b1;
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default:trigger_CAVLC <= 1'b0;
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default:trigger_CAVLC <= 1'b0;
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endcase
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endcase
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// End of skip or normal
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// End of skip or normal
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else if (end_of_one_blk4x4_sum)
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else if (end_of_one_blk4x4_sum)
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begin
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begin
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if (slice_data_state == `skip_run_duration)
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if (slice_data_state == `skip_run_duration)
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trigger_CAVLC <= 1'b0;
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trigger_CAVLC <= 1'b0;
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else
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else
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case (blk4x4_rec_counter)
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case (blk4x4_rec_counter)
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0,1,2,4,5,6,8,9,10,12,13,14:trigger_CAVLC <= (curr_CBPLuma_IsZero)? 1'b0:1'b1;
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0,1,2,4,5,6,8,9,10,12,13,14:trigger_CAVLC <= (curr_CBPLuma_IsZero)? 1'b0:1'b1;
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3 :trigger_CAVLC <= (CodedBlockPatternLuma[1])? 1'b1:1'b0;
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3 :trigger_CAVLC <= (CodedBlockPatternLuma[1])? 1'b1:1'b0;
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7 :trigger_CAVLC <= (CodedBlockPatternLuma[2])? 1'b1:1'b0;
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7 :trigger_CAVLC <= (CodedBlockPatternLuma[2])? 1'b1:1'b0;
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11:trigger_CAVLC <= (CodedBlockPatternLuma[3])? 1'b1:1'b0;
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11:trigger_CAVLC <= (CodedBlockPatternLuma[3])? 1'b1:1'b0;
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15:trigger_CAVLC <= (CodedBlockPatternChroma == 0)? 1'b0:1'b1;
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15:trigger_CAVLC <= (CodedBlockPatternChroma == 0)? 1'b0:1'b1;
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23:trigger_CAVLC <= 1'b0;
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23:trigger_CAVLC <= 1'b0;
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default:trigger_CAVLC <= (CodedBlockPatternChroma == 2)? 1'b1:1'b0;
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default:trigger_CAVLC <= (CodedBlockPatternChroma == 2)? 1'b1:1'b0;
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endcase
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endcase
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end
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end
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else
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else
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trigger_CAVLC <= 1'b0;
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trigger_CAVLC <= 1'b0;
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//end_of_MB_rec:end of one MB reconstruction
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//end_of_MB_rec:end of one MB reconstruction
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wire end_of_MB_rec;
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wire end_of_MB_rec;
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assign end_of_MB_rec = (blk4x4_rec_counter == 5'd23 && end_of_one_blk4x4_sum == 1'b1)? 1'b1:1'b0;
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assign end_of_MB_rec = (blk4x4_rec_counter == 5'd23 && end_of_one_blk4x4_sum == 1'b1)? 1'b1:1'b0;
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//MB_needs_DF: identify whether this MB needs to be deblocking filtered
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//MB_needs_DF: identify whether this MB needs to be deblocking filtered
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reg MB_needs_DF;
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reg MB_needs_DF;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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MB_needs_DF <= 1'b0;
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MB_needs_DF <= 1'b0;
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else if (end_of_MB_DEC == 1'b1 && !disable_DF)
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else if (end_of_MB_DEC == 1'b1 && !disable_DF)
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MB_needs_DF <= 1'b1;
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MB_needs_DF <= 1'b1;
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else if (end_of_MB_DEC == 1'b1 && disable_DF)
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else if (end_of_MB_DEC == 1'b1 && disable_DF)
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MB_needs_DF <= 1'b0;
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MB_needs_DF <= 1'b0;
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//MB_rec_DF_align:latch the first arrival of end_of_MB_rec and end_of_MB_DF
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//MB_rec_DF_align:latch the first arrival of end_of_MB_rec and end_of_MB_DF
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reg MB_rec_DF_align;
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reg MB_rec_DF_align;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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MB_rec_DF_align <= 1'b0;
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MB_rec_DF_align <= 1'b0;
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else if (end_of_MB_DEC)
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else if (end_of_MB_DEC)
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MB_rec_DF_align <= 1'b0;
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MB_rec_DF_align <= 1'b0;
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else if (MB_needs_DF && (end_of_MB_rec || end_of_MB_DF == 1'b1))
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else if (MB_needs_DF && (end_of_MB_rec || end_of_MB_DF == 1'b1))
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MB_rec_DF_align <= 1'b1;
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MB_rec_DF_align <= 1'b1;
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//end_of_MB_DEC:end of one macroblock decoding (end of both reconstruction and previous MB's deblocking
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//end_of_MB_DEC:end of one macroblock decoding (end of both reconstruction and previous MB's deblocking
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// (if previous MB needs deblocking)),generated by combinational logic
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// (if previous MB needs deblocking)),generated by combinational logic
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reg end_of_MB_DEC;
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reg end_of_MB_DEC;
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always @ (MB_needs_DF or end_of_MB_rec or end_of_MB_DF or MB_rec_DF_align or mb_num_h or mb_num_v)
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always @ (MB_needs_DF or end_of_MB_rec or end_of_MB_DF or MB_rec_DF_align or mb_num_h or mb_num_v)
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if (MB_needs_DF == 1'b1)
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if (MB_needs_DF == 1'b1)
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begin
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begin
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if (end_of_MB_rec && end_of_MB_DF) //arrive simultaneously
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if (end_of_MB_rec && end_of_MB_DF) //arrive simultaneously
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end_of_MB_DEC <= 1'b1;
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end_of_MB_DEC <= 1'b1;
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else if (MB_rec_DF_align == 1'b1 && (end_of_MB_rec || end_of_MB_DF))
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else if (MB_rec_DF_align == 1'b1 && (end_of_MB_rec || end_of_MB_DF))
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end_of_MB_DEC <= 1'b1;
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end_of_MB_DEC <= 1'b1;
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else if (mb_num_h == 0 && mb_num_v == 0 && end_of_MB_rec)//first MB has no correspinding DF process
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else if (mb_num_h == 0 && mb_num_v == 0 && end_of_MB_rec)//first MB has no correspinding DF process
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end_of_MB_DEC <= 1'b1;
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end_of_MB_DEC <= 1'b1;
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else
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else
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end_of_MB_DEC <= 1'b0;
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end_of_MB_DEC <= 1'b0;
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end
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end
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else
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else
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end_of_MB_DEC <= (end_of_MB_rec)? 1'b1:1'b0;
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end_of_MB_DEC <= (end_of_MB_rec)? 1'b1:1'b0;
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//2. trigger_blk4x4_intra_pred
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//2. trigger_blk4x4_intra_pred
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wire trigger_blk4x4_intra_pred_tmp;
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wire trigger_blk4x4_intra_pred_tmp;
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assign trigger_blk4x4_intra_pred_tmp = (mb_type_general[3] && ((slice_data_state == `residual &&
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assign trigger_blk4x4_intra_pred_tmp = (mb_type_general[3] && ((slice_data_state == `residual &&
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residual_state == `rst_residual) || (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)))? 1'b1:1'b0;
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residual_state == `rst_residual) || (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)))? 1'b1:1'b0;
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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trigger_blk4x4_intra_pred <= 1'b0;
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trigger_blk4x4_intra_pred <= 1'b0;
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else
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else
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trigger_blk4x4_intra_pred <= trigger_blk4x4_intra_pred_tmp;
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trigger_blk4x4_intra_pred <= trigger_blk4x4_intra_pred_tmp;
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//3. trigger_blk4x4_inter_pred
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//3. trigger_blk4x4_inter_pred
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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trigger_blk4x4_inter_pred <= 1'b0;
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trigger_blk4x4_inter_pred <= 1'b0;
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//For skip_run_duration
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//For skip_run_duration
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// 1.trigger inter pred when entering skip_run_duration after mb_skip_run_s state
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// 1.trigger inter pred when entering skip_run_duration after mb_skip_run_s state
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else if (Is_skip_run_entry)
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else if (Is_skip_run_entry)
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trigger_blk4x4_inter_pred <= 1'b1;
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trigger_blk4x4_inter_pred <= 1'b1;
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// 2.trigger inter pred during skip_run_duration
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// 2.trigger inter pred during skip_run_duration
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else if (slice_data_state == `skip_run_duration)
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else if (slice_data_state == `skip_run_duration)
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begin
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begin
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if (skip_mv_calc)
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if (skip_mv_calc)
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trigger_blk4x4_inter_pred <= 1'b1;
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trigger_blk4x4_inter_pred <= 1'b1;
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else
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else
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trigger_blk4x4_inter_pred <= (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)? 1'b1:1'b0;
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trigger_blk4x4_inter_pred <= (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)? 1'b1:1'b0;
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end
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end
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//For normal case:inside residual_state
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//For normal case:inside residual_state
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// 1.entry
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// 1.entry
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else if (slice_data_state == `residual && residual_state == `rst_residual && !mb_type_general[3])
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else if (slice_data_state == `residual && residual_state == `rst_residual && !mb_type_general[3])
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trigger_blk4x4_inter_pred <= 1'b1;
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trigger_blk4x4_inter_pred <= 1'b1;
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// 2.end of normal
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// 2.end of normal
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else if (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23 && !mb_type_general[3])
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else if (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23 && !mb_type_general[3])
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trigger_blk4x4_inter_pred <= 1'b1;
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trigger_blk4x4_inter_pred <= 1'b1;
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else
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else
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trigger_blk4x4_inter_pred <= 1'b0;
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trigger_blk4x4_inter_pred <= 1'b0;
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//4. trigger reconstruction sum
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//4. trigger reconstruction sum
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// Need to align the output of residual(IQIT) and predition(inter/intra)
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// Need to align the output of residual(IQIT) and predition(inter/intra)
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wire end_of_one_blk4x4_pred;
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wire end_of_one_blk4x4_pred;
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wire end_of_one_blk4x4_res; //end of one zero or non-zero AC blk4x4 IQIT (NOT DC!)
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wire end_of_one_blk4x4_res; //end of one zero or non-zero AC blk4x4 IQIT (NOT DC!)
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reg blk4x4_res_pred_align;
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reg blk4x4_res_pred_align;
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assign end_of_one_blk4x4_pred = (end_of_one_blk4x4_inter || end_of_one_blk4x4_intra);
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assign end_of_one_blk4x4_pred = (end_of_one_blk4x4_inter || end_of_one_blk4x4_intra);
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assign end_of_one_blk4x4_res = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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assign end_of_one_blk4x4_res = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) &&
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) &&
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(end_of_one_residual_block && TotalCoeff == 0)) || end_of_ACBlk4x4_IQIT)? 1'b1:1'b0;
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(end_of_one_residual_block && TotalCoeff == 0)) || end_of_ACBlk4x4_IQIT)? 1'b1:1'b0;
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//align the completion of prediction and residual decoding
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//align the completion of prediction and residual decoding
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always @ (posedge clk)
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always @ (posedge clk)
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if (reset_n == 1'b0)
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if (reset_n == 1'b0)
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blk4x4_res_pred_align <= 0;
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blk4x4_res_pred_align <= 0;
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else if (trigger_blk4x4_rec_sum == 1'b1)
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else if (trigger_blk4x4_rec_sum == 1'b1)
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blk4x4_res_pred_align <= 1'b0;
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blk4x4_res_pred_align <= 1'b0;
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else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously,no align
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else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously,no align
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blk4x4_res_pred_align <= 1'b0;
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blk4x4_res_pred_align <= 1'b0;
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else if (end_of_one_blk4x4_res || end_of_one_blk4x4_pred)
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else if (end_of_one_blk4x4_res || end_of_one_blk4x4_pred)
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blk4x4_res_pred_align <= 1'b1;
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blk4x4_res_pred_align <= 1'b1;
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always @ (slice_data_state or residual_state or curr_CBPLuma_IsZero or blk4x4_res_pred_align or
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always @ (slice_data_state or residual_state or curr_CBPLuma_IsZero or blk4x4_res_pred_align or
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end_of_one_blk4x4_pred or end_of_one_blk4x4_res)
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end_of_one_blk4x4_pred or end_of_one_blk4x4_res)
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if (slice_data_state == `skip_run_duration)
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if (slice_data_state == `skip_run_duration)
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trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred)? 1'b1:1'b0;
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trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred)? 1'b1:1'b0;
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// Normal
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// Normal
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else if (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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else if (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)
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begin
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begin
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if (curr_CBPLuma_IsZero)
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if (curr_CBPLuma_IsZero)
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trigger_blk4x4_rec_sum <= (blk4x4_res_pred_align)? 1'b1:end_of_one_blk4x4_pred;
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trigger_blk4x4_rec_sum <= (blk4x4_res_pred_align)? 1'b1:end_of_one_blk4x4_pred;
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else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously
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else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously
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trigger_blk4x4_rec_sum <= 1'b1;
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trigger_blk4x4_rec_sum <= 1'b1;
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else if ((end_of_one_blk4x4_res || end_of_one_blk4x4_pred) && blk4x4_res_pred_align)
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else if ((end_of_one_blk4x4_res || end_of_one_blk4x4_pred) && blk4x4_res_pred_align)
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trigger_blk4x4_rec_sum <= 1'b1;
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trigger_blk4x4_rec_sum <= 1'b1;
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else
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else
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trigger_blk4x4_rec_sum <= 1'b0;
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trigger_blk4x4_rec_sum <= 1'b0;
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end
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end
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// zero blocks
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// zero blocks
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else if (residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_0_s
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else if (residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_0_s
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|| residual_state == `ChromaACLevel_0_s)
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|| residual_state == `ChromaACLevel_0_s)
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trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred || blk4x4_res_pred_align)? 1'b1:1'b0;
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trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred || blk4x4_res_pred_align)? 1'b1:1'b0;
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else
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else
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trigger_blk4x4_rec_sum <= 1'b0;
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trigger_blk4x4_rec_sum <= 1'b0;
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//5.trigger Deblocking Filter
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//5.trigger Deblocking Filter
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//assign trigger_MB_DF = (end_of_MB_DEC == 1'b1 && !disable_DF)? 1'b1:1'b0;
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//assign trigger_MB_DF = (end_of_MB_DEC == 1'b1 && !disable_DF)? 1'b1:1'b0;
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endmodule
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endmodule
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