//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : ram_sync_1r_sync_1w.v
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// File : ram_sync_1r_sync_1w.v
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// Generated : April 25,2005
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// Generated : April 25,2005
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Synch Write, Synch Read RAM, NOT synthesizable
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// Synch Write, Synch Read RAM, NOT synthesizable
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// In real silicon, use customized RAM instead of DFF
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// In real silicon, use customized RAM instead of DFF
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// legal range:data_width [ 1 to 256 ]
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// legal range:data_width [ 1 to 256 ]
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// legal range:data_depth [ 2 to 1024 ]
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// legal range:data_depth [ 2 to 1024 ]
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// Input data :data_in[data_width-1:0]
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// Input data :data_in[data_width-1:0]
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// Output data:data_out[data_width-1:0]
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// Output data:data_out[data_width-1:0]
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// Read Address :rd_addr[addr_width-1:0]
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// Read Address :rd_addr[addr_width-1:0]
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// Write Address:wr_addr[addr_width-1:0]
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// Write Address:wr_addr[addr_width-1:0]
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// Write enable (active low): wr_n
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// Write enable (active low): wr_n
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// Chip select (active low): cs_n
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// Chip select (active low): cs_n
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// Reset (active low): rst_n
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// Reset (active low): rst_n
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// Clock:clk
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// Clock:clk
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module ram_sync_1r_sync_1w (clk, rst_n, wr_n, rd_n, wr_addr, rd_addr, data_in, data_out);
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module ram_sync_1r_sync_1w (clk, rst_n, wr_n, rd_n, wr_addr, rd_addr, data_in, data_out);
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parameter data_width = 4; //will be overrided during module instantiation
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parameter data_width = 4; //will be overrided during module instantiation
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parameter data_depth = 8; //will be overrided during module instantiation
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parameter data_depth = 8; //will be overrided during module instantiation
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`define addr_width ((data_depth>32)?((data_depth>256)?((data_depth>512)?10:9):((data_depth>128)?8:((data_depth>64)?7:6))):((data_depth>8) ?((data_depth>16) ?5:4) :((data_depth>4) ?3:((data_depth>2) ?1:0))))
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`define addr_width ((data_depth>32)?((data_depth>256)?((data_depth>512)?10:9):((data_depth>128)?8:((data_depth>64)?7:6))):((data_depth>8) ?((data_depth>16) ?5:4) :((data_depth>4) ?3:((data_depth>2) ?1:0))))
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input clk;
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input clk;
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input rst_n;
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input rst_n;
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input wr_n;
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input wr_n;
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input rd_n;
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input rd_n;
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input [`addr_width-1:0] wr_addr;
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input [`addr_width-1:0] wr_addr;
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input [`addr_width-1:0] rd_addr;
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input [`addr_width-1:0] rd_addr;
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input [data_width-1:0] data_in;
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input [data_width-1:0] data_in;
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output [data_width-1:0] data_out;
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output [data_width-1:0] data_out;
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reg [data_width-1:0] data_out;
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reg [data_width-1:0] data_out;
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reg [data_width-1:0] ram [data_depth-1:0];
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reg [data_width-1:0] ram [data_depth-1:0];
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//data_width, data_depth, simultaneously read/write check
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//data_width, data_depth, simultaneously read/write check
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initial
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initial
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begin:parameter_check
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begin:parameter_check
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integer param_error_flag;
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integer param_error_flag;
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param_error_flag = 0;
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param_error_flag = 0;
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if ( (data_width < 1) || (data_width > 256) )
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if ( (data_width < 1) || (data_width > 256) )
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begin
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begin
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param_error_flag = 1;
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param_error_flag = 1;
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$display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 256)",data_width );
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$display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 256)",data_width );
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end
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end
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if ( (data_depth < 2) || (data_depth > 1024 ) )
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if ( (data_depth < 2) || (data_depth > 1024 ) )
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begin
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begin
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param_error_flag = 1;
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param_error_flag = 1;
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$display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 1024 )",data_depth );
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$display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 1024 )",data_depth );
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end
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end
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/*
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/*
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if ( (cs_n == 1'b0 && wr_n == 1'b0 && rd_n == 1'b0 ) )
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if ( (cs_n == 1'b0 && wr_n == 1'b0 && rd_n == 1'b0 ) )
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begin
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begin
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param_error_flag = 1;
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param_error_flag = 1;
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$display("Error: %m :\n Not allowed! RAM simultaneously read and write occur");
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$display("Error: %m :\n Not allowed! RAM simultaneously read and write occur");
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end
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end
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*/
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*/
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if ( param_error_flag == 1)
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if ( param_error_flag == 1)
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begin
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begin
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$display("%m :\n Simulation aborted due to invalid parameter value(s)");
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$display("%m :\n Simulation aborted due to invalid parameter value(s)");
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$finish;
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$finish;
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end
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end
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end // end data_width & data_depth check
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end // end data_width & data_depth check
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//read
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//read
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always @ (posedge clk or negedge rst_n)
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always @ (posedge clk or negedge rst_n)
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if (rst_n == 1'b0)
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if (rst_n == 1'b0)
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data_out <= 0;
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data_out <= 0;
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else if (!rd_n)
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else if (!rd_n)
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data_out <= ram[rd_addr];
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data_out <= ram[rd_addr];
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//write
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//write
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always @ (posedge clk)
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always @ (posedge clk)
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if (!wr_n)
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if (!wr_n)
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ram[wr_addr] <= data_in;
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ram[wr_addr] <= data_in;
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endmodule
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endmodule
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