//--------------------------------------------------------------------------------------------------
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//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Design : nova
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// Author(s) : Ke Xu
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// Email : eexuke@yahoo.com
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// File : rec_gclk_gen.v
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// File : rec_gclk_gen.v
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// Generated : Jan 3, 2006
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// Generated : Jan 3, 2006
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// Copyright (C) 2008 Ke Xu
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// Description
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// Description
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// Gated clock generation module for reconstruction
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// Gated clock generation module for reconstruction
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "nova_defines.v"
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`include "nova_defines.v"
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module rec_gclk_gen(clk,
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module rec_gclk_gen(clk,
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//IQIT
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//IQIT
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end_of_NonZeroCoeff_CAVLC,OneD_counter,TwoD_counter,rescale_counter,
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end_of_NonZeroCoeff_CAVLC,OneD_counter,TwoD_counter,rescale_counter,
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rounding_counter,residual_state,cavlc_decoder_state,
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rounding_counter,residual_state,cavlc_decoder_state,
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gclk_1D,gclk_2D,gclk_rescale,gclk_rounding,
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gclk_1D,gclk_2D,gclk_rescale,gclk_rounding,
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//Intra pred
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//Intra pred
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mb_num_h,mb_num_v,NextMB_IsSkip,
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mb_num_h,mb_num_v,NextMB_IsSkip,
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mb_type_general,blk4x4_rec_counter,blk4x4_sum_counter,blk4x4_intra_preload_counter,
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mb_type_general,blk4x4_rec_counter,blk4x4_sum_counter,blk4x4_intra_preload_counter,
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blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
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Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
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Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
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gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,
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gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,
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gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
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gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,
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//Inter pred
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//Inter pred
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blk4x4_inter_preload_counter,gclk_Inter_ref_rf,
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blk4x4_inter_preload_counter,gclk_Inter_ref_rf,
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//sum
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//sum
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Inter_blk4x4_pred_output_valid,gclk_pred_output,gclk_blk4x4_sum,
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Inter_blk4x4_pred_output_valid,gclk_pred_output,gclk_blk4x4_sum,
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//Deblocking filter
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//Deblocking filter
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end_of_MB_DEC,end_of_BS_DEC,DF_duration,
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end_of_MB_DEC,end_of_BS_DEC,DF_duration,
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gclk_end_of_MB_DEC,gclk_DF,
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gclk_end_of_MB_DEC,gclk_DF,
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//memory
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//memory
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Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_wr,gclk_Intra_mbAddrB_RAM,
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Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_wr,gclk_Intra_mbAddrB_RAM,
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rec_DF_RAM0_cs_n,gclk_rec_DF_RAM0,
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rec_DF_RAM0_cs_n,gclk_rec_DF_RAM0,
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rec_DF_RAM1_cs_n,gclk_rec_DF_RAM1,
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rec_DF_RAM1_cs_n,gclk_rec_DF_RAM1,
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DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,gclk_DF_mbAddrA_RF,
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DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,gclk_DF_mbAddrA_RF,
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DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,gclk_DF_mbAddrB_RAM
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DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,gclk_DF_mbAddrB_RAM
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);
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);
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input clk;
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input clk;
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//IQIT
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//IQIT
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input end_of_NonZeroCoeff_CAVLC;
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input end_of_NonZeroCoeff_CAVLC;
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input [2:0] OneD_counter;
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input [2:0] OneD_counter;
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input [2:0] TwoD_counter;
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input [2:0] TwoD_counter;
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input [2:0] rescale_counter;
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input [2:0] rescale_counter;
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input [2:0] rounding_counter;
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input [2:0] rounding_counter;
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input [3:0] residual_state;
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input [3:0] residual_state;
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input [3:0] cavlc_decoder_state;
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input [3:0] cavlc_decoder_state;
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output gclk_1D;
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output gclk_1D;
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output gclk_2D;
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output gclk_2D;
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output gclk_rescale;
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output gclk_rescale;
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output gclk_rounding;
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output gclk_rounding;
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//Intra pred
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//Intra pred
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input [3:0] mb_num_h;
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input [3:0] mb_num_h;
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input [3:0] mb_num_v;
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input [3:0] mb_num_v;
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input NextMB_IsSkip;
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input NextMB_IsSkip;
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input [3:0] mb_type_general;
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input [3:0] mb_type_general;
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input [4:0] blk4x4_rec_counter;
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input [4:0] blk4x4_rec_counter;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_sum_counter;
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input [2:0] blk4x4_intra_preload_counter;
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input [2:0] blk4x4_intra_preload_counter;
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input [3:0] blk4x4_intra_precompute_counter;
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input [3:0] blk4x4_intra_precompute_counter;
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input [2:0] blk4x4_intra_calculate_counter;
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input [2:0] blk4x4_intra_calculate_counter;
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input [3:0] Intra4x4_predmode;
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input [3:0] Intra4x4_predmode;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra_chroma_predmode;
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input [1:0] Intra_chroma_predmode;
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output gclk_intra_mbAddrA_luma;
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output gclk_intra_mbAddrA_luma;
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output gclk_intra_mbAddrA_Cb;
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output gclk_intra_mbAddrA_Cb;
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output gclk_intra_mbAddrA_Cr;
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output gclk_intra_mbAddrA_Cr;
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output gclk_intra_mbAddrB;
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output gclk_intra_mbAddrB;
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output gclk_intra_mbAddrC_luma;
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output gclk_intra_mbAddrC_luma;
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output gclk_intra_mbAddrD;
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output gclk_intra_mbAddrD;
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output gclk_seed;
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output gclk_seed;
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//Inter pred
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//Inter pred
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input [5:0] blk4x4_inter_preload_counter;
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input [5:0] blk4x4_inter_preload_counter;
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output gclk_Inter_ref_rf;
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output gclk_Inter_ref_rf;
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//sum
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//sum
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input [1:0] Inter_blk4x4_pred_output_valid;
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input [1:0] Inter_blk4x4_pred_output_valid;
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output gclk_pred_output;
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output gclk_pred_output;
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output gclk_blk4x4_sum;
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output gclk_blk4x4_sum;
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//DF
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//DF
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input end_of_MB_DEC;
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input end_of_MB_DEC;
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input end_of_BS_DEC;
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input end_of_BS_DEC;
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input DF_duration;
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input DF_duration;
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output gclk_end_of_MB_DEC;
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output gclk_end_of_MB_DEC;
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output gclk_DF;
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output gclk_DF;
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//memory
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//memory
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input Intra_mbAddrB_RAM_rd;
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input Intra_mbAddrB_RAM_rd;
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input Intra_mbAddrB_RAM_wr;
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input Intra_mbAddrB_RAM_wr;
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output gclk_Intra_mbAddrB_RAM;
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output gclk_Intra_mbAddrB_RAM;
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input rec_DF_RAM0_cs_n;
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input rec_DF_RAM0_cs_n;
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output gclk_rec_DF_RAM0;
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output gclk_rec_DF_RAM0;
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input rec_DF_RAM1_cs_n;
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input rec_DF_RAM1_cs_n;
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output gclk_rec_DF_RAM1;
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output gclk_rec_DF_RAM1;
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input DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr;
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input DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr;
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output gclk_DF_mbAddrA_RF;
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output gclk_DF_mbAddrA_RF;
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input DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
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input DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr;
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output gclk_DF_mbAddrB_RAM;
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output gclk_DF_mbAddrB_RAM;
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parameter rst_residual = 4'b0000;
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parameter rst_residual = 4'b0000;
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parameter Intra16x16DCLevel_s = 4'b0001;
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parameter Intra16x16DCLevel_s = 4'b0001;
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parameter Intra16x16ACLevel_s = 4'b0011;
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parameter Intra16x16ACLevel_s = 4'b0011;
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parameter Intra16x16ACLevel_0_s = 4'b0010;
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parameter Intra16x16ACLevel_0_s = 4'b0010;
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parameter LumaLevel_s = 4'b0110;
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parameter LumaLevel_s = 4'b0110;
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parameter LumaLevel_0_s = 4'b0111;
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parameter LumaLevel_0_s = 4'b0111;
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parameter ChromaDCLevel_Cb_s = 4'b0101;
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parameter ChromaDCLevel_Cb_s = 4'b0101;
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parameter ChromaDCLevel_Cr_s = 4'b0100;
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parameter ChromaDCLevel_Cr_s = 4'b0100;
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parameter ChromaACLevel_Cb_s = 4'b1100;
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parameter ChromaACLevel_Cb_s = 4'b1100;
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parameter ChromaACLevel_Cr_s = 4'b1101;
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parameter ChromaACLevel_Cr_s = 4'b1101;
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parameter Intra4x4_Vertical = 4'b0000;
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parameter Intra4x4_Vertical = 4'b0000;
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parameter Intra4x4_Horizontal = 4'b0001;
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parameter Intra4x4_Horizontal = 4'b0001;
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parameter Intra4x4_DC = 4'b0010;
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parameter Intra4x4_DC = 4'b0010;
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parameter Intra4x4_Diagonal_Down_Left = 4'b0011;
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parameter Intra4x4_Diagonal_Down_Left = 4'b0011;
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parameter Intra4x4_Diagonal_Down_Right = 4'b0100;
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parameter Intra4x4_Diagonal_Down_Right = 4'b0100;
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parameter Intra4x4_Vertical_Right = 4'b0101;
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parameter Intra4x4_Vertical_Right = 4'b0101;
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parameter Intra4x4_Horizontal_Down = 4'b0110;
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parameter Intra4x4_Horizontal_Down = 4'b0110;
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parameter Intra4x4_Vertical_Left = 4'b0111;
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parameter Intra4x4_Vertical_Left = 4'b0111;
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parameter Intra4x4_Horizontal_Up = 4'b1000;
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parameter Intra4x4_Horizontal_Up = 4'b1000;
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parameter Intra16x16_Plane = 2'b11;
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parameter Intra16x16_Plane = 2'b11;
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parameter Intra_chroma_Plane = 2'b11;
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parameter Intra_chroma_Plane = 2'b11;
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parameter NumCoeffTrailingOnes_LUT = 4'b0010;
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parameter NumCoeffTrailingOnes_LUT = 4'b0010;
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//-------------------------------------------------
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//-------------------------------------------------
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//IQIT
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//IQIT
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//-------------------------------------------------
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//-------------------------------------------------
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//gclk_end_of_one_residual_block
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//gclk_end_of_one_residual_block
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//reg l_end_of_one_residual_block;
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//reg l_end_of_one_residual_block;
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//wire gclk_end_of_one_residual_block;
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//wire gclk_end_of_one_residual_block;
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//always @ (clk or end_of_one_residual_block)
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//always @ (clk or end_of_one_residual_block)
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// if (!clk) l_end_of_one_residual_block <= end_of_one_residual_block;
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// if (!clk) l_end_of_one_residual_block <= end_of_one_residual_block;
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//assign gclk_end_of_one_residual_block = clk & l_end_of_one_residual_block;
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//assign gclk_end_of_one_residual_block = clk & l_end_of_one_residual_block;
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//gclk_endof1NonZeroCoeffResBlk
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//gclk_endof1NonZeroCoeffResBlk
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//reg l_end_of_NonZeroCoeff_CAVLC;
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//reg l_end_of_NonZeroCoeff_CAVLC;
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//wire gclk_endof1NonZeroCoeffResBlk;
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//wire gclk_endof1NonZeroCoeffResBlk;
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//always @ (clk or end_of_NonZeroCoeff_CAVLC)
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//always @ (clk or end_of_NonZeroCoeff_CAVLC)
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// if (!clk) l_end_of_NonZeroCoeff_CAVLC <= end_of_NonZeroCoeff_CAVLC;
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// if (!clk) l_end_of_NonZeroCoeff_CAVLC <= end_of_NonZeroCoeff_CAVLC;
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//assign gclk_endof1NonZeroCoeffResBlk = clk & l_end_of_NonZeroCoeff_CAVLC;
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//assign gclk_endof1NonZeroCoeffResBlk = clk & l_end_of_NonZeroCoeff_CAVLC;
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//gclk_1D
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//gclk_1D
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wire OneD_en;
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wire OneD_en;
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reg l_OneD_en;
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reg l_OneD_en;
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wire gclk_1D;
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wire gclk_1D;
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assign OneD_en = (
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assign OneD_en = (
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// trap DC case after CAVLC:residual_state is still available now
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// trap DC case after CAVLC:residual_state is still available now
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(end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT &&
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(end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT &&
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(residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
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(residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s ||
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residual_state == `ChromaDCLevel_Cr_s)) ||
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residual_state == `ChromaDCLevel_Cr_s)) ||
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// trap AC case after rescale:residual_state is still available now
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// trap AC case after rescale:residual_state is still available now
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((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || residual_state == `ChromaACLevel_Cb_s ||
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((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || residual_state == `ChromaACLevel_Cb_s ||
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residual_state == `ChromaACLevel_Cr_s) && rescale_counter == 3'b100) ||
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residual_state == `ChromaACLevel_Cr_s) && rescale_counter == 3'b100) ||
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// trap internal loop
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// trap internal loop
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OneD_counter != 0);
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OneD_counter != 0);
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always @ (clk or OneD_en)
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always @ (clk or OneD_en)
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if (!clk) l_OneD_en <= OneD_en;
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if (!clk) l_OneD_en <= OneD_en;
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assign gclk_1D = clk & l_OneD_en;
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assign gclk_1D = clk & l_OneD_en;
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//gclk_2D
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//gclk_2D
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wire TwoD_en;
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wire TwoD_en;
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reg l_TwoD_en;
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reg l_TwoD_en;
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wire gclk_2D;
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wire gclk_2D;
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assign TwoD_en = ((OneD_counter == 3'b001 && residual_state != `ChromaDCLevel_Cb_s && residual_state != `ChromaDCLevel_Cr_s)
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assign TwoD_en = ((OneD_counter == 3'b001 && residual_state != `ChromaDCLevel_Cb_s && residual_state != `ChromaDCLevel_Cr_s)
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|| TwoD_counter != 0);
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|| TwoD_counter != 0);
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always @ (clk or TwoD_en)
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always @ (clk or TwoD_en)
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if (!clk) l_TwoD_en <= TwoD_en;
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if (!clk) l_TwoD_en <= TwoD_en;
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assign gclk_2D = clk & l_TwoD_en;
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assign gclk_2D = clk & l_TwoD_en;
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//gclk_rescale
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//gclk_rescale
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wire rescale_en;
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wire rescale_en;
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reg l_rescale_en;
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reg l_rescale_en;
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wire gclk_rescale;
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wire gclk_rescale;
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assign rescale_en = (
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assign rescale_en = (
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//trap AC after CAVLC except all zero coeffs case
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//trap AC after CAVLC except all zero coeffs case
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(end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && (
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(end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && (
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residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)) ||
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)) ||
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//trap DC case after IDCT,chromaDC:after 1D-IDCT,lumaDC:after 2D-IDCT
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//trap DC case after IDCT,chromaDC:after 1D-IDCT,lumaDC:after 2D-IDCT
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((residual_state == `Intra16x16DCLevel_s && TwoD_counter == 3'b100) ||
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((residual_state == `Intra16x16DCLevel_s && TwoD_counter == 3'b100) ||
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((residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) && OneD_counter == 3'b001)) ||
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((residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) && OneD_counter == 3'b001)) ||
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//trap internal loop
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//trap internal loop
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rescale_counter != 0);
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rescale_counter != 0);
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always @ (clk or rescale_en)
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always @ (clk or rescale_en)
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if (!clk) l_rescale_en <= rescale_en;
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if (!clk) l_rescale_en <= rescale_en;
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and gc_rescale (gclk_rescale,clk,l_rescale_en);
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and gc_rescale (gclk_rescale,clk,l_rescale_en);
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//gclk_rounding
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//gclk_rounding
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wire rounding_en;
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wire rounding_en;
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reg l_rounding_en;
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reg l_rounding_en;
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wire gclk_rounding;
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wire gclk_rounding;
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assign rounding_en = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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assign rounding_en = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s ||
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && TwoD_counter == 3'b100)
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residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && TwoD_counter == 3'b100)
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|| rounding_counter !=0)?1'b1:1'b0;
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|| rounding_counter !=0)?1'b1:1'b0;
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always @ (clk or rounding_en)
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always @ (clk or rounding_en)
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if (!clk) l_rounding_en <= rounding_en;
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if (!clk) l_rounding_en <= rounding_en;
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assign gclk_rounding = clk & l_rounding_en;
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assign gclk_rounding = clk & l_rounding_en;
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//-------------------------------------------------
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//-------------------------------------------------
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//Intra pred
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//Intra pred
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//-------------------------------------------------
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//-------------------------------------------------
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//1.gclk_intra_mbAddrA_luma @ Intra_pred_reg_ctrl.v
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//1.gclk_intra_mbAddrA_luma @ Intra_pred_reg_ctrl.v
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// For intra pred,update after every blk4x4 is summed
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// For intra pred,update after every blk4x4 is summed
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// For inter pred,update after blk4x4 5,7,13,15 is summed
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// For inter pred,update after blk4x4 5,7,13,15 is summed
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wire intra_mbAddrA_luma_ena;
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wire intra_mbAddrA_luma_ena;
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reg l_intra_mbAddrA_luma_ena;
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reg l_intra_mbAddrA_luma_ena;
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wire gclk_intra_mbAddrA_luma;
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wire gclk_intra_mbAddrA_luma;
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wire Is_LumaRightMostBlk4x4;
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wire Is_LumaRightMostBlk4x4;
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assign Is_LumaRightMostBlk4x4 = (blk4x4_rec_counter == 5 || blk4x4_rec_counter == 7 ||
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assign Is_LumaRightMostBlk4x4 = (blk4x4_rec_counter == 5 || blk4x4_rec_counter == 7 ||
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blk4x4_rec_counter == 13 || blk4x4_rec_counter == 15);
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blk4x4_rec_counter == 13 || blk4x4_rec_counter == 15);
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assign intra_mbAddrA_luma_ena = (blk4x4_rec_counter < 16 && blk4x4_sum_counter == 3'd3 && (
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assign intra_mbAddrA_luma_ena = (blk4x4_rec_counter < 16 && blk4x4_sum_counter == 3'd3 && (
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//Intra4x4:update when every blk4x4 summed
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//Intra4x4:update when every blk4x4 summed
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(mb_type_general[3:2] == 2'b11 && !(mb_num_h == 10 && Is_LumaRightMostBlk4x4)) ||
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(mb_type_general[3:2] == 2'b11 && !(mb_num_h == 10 && Is_LumaRightMostBlk4x4)) ||
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//Intra16x16 && Inter (including skip MB):update when blk4x4 5/7/13/15 is summed
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//Intra16x16 && Inter (including skip MB):update when blk4x4 5/7/13/15 is summed
|
//and NextMB_IsSkip is false
|
//and NextMB_IsSkip is false
|
(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_LumaRightMostBlk4x4 && !NextMB_IsSkip)));
|
(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_LumaRightMostBlk4x4 && !NextMB_IsSkip)));
|
always @ (clk or intra_mbAddrA_luma_ena)
|
always @ (clk or intra_mbAddrA_luma_ena)
|
if (!clk) l_intra_mbAddrA_luma_ena <= intra_mbAddrA_luma_ena;
|
if (!clk) l_intra_mbAddrA_luma_ena <= intra_mbAddrA_luma_ena;
|
assign gclk_intra_mbAddrA_luma = l_intra_mbAddrA_luma_ena & clk;
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assign gclk_intra_mbAddrA_luma = l_intra_mbAddrA_luma_ena & clk;
|
|
|
//2.gclk_intra_mbAddrA_Cb @ Intra_pred_reg_ctrl.v
|
//2.gclk_intra_mbAddrA_Cb @ Intra_pred_reg_ctrl.v
|
wire intra_mbAddrA_Cb_ena;
|
wire intra_mbAddrA_Cb_ena;
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reg l_intra_mbAddrA_Cb_ena;
|
reg l_intra_mbAddrA_Cb_ena;
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wire gclk_intra_mbAddrA_Cb;
|
wire gclk_intra_mbAddrA_Cb;
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wire Is_CbRightMostBlk4x4;
|
wire Is_CbRightMostBlk4x4;
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assign Is_CbRightMostBlk4x4 = (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 19);
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assign Is_CbRightMostBlk4x4 = (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 19);
|
|
|
assign intra_mbAddrA_Cb_ena = (blk4x4_sum_counter == 3'd3 && (
|
assign intra_mbAddrA_Cb_ena = (blk4x4_sum_counter == 3'd3 && (
|
//Intra4x4
|
//Intra4x4
|
(mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4) ||
|
(mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4) ||
|
//Intra16x16 && Inter (including skip MB)
|
//Intra16x16 && Inter (including skip MB)
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(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4 && !NextMB_IsSkip)));
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(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4 && !NextMB_IsSkip)));
|
always @ (clk or intra_mbAddrA_Cb_ena)
|
always @ (clk or intra_mbAddrA_Cb_ena)
|
if (!clk) l_intra_mbAddrA_Cb_ena <= intra_mbAddrA_Cb_ena;
|
if (!clk) l_intra_mbAddrA_Cb_ena <= intra_mbAddrA_Cb_ena;
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assign gclk_intra_mbAddrA_Cb = l_intra_mbAddrA_Cb_ena & clk;
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assign gclk_intra_mbAddrA_Cb = l_intra_mbAddrA_Cb_ena & clk;
|
|
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//3.gclk_intra_mbAddrA_Cr @ Intra_pred_reg_ctrl.v
|
//3.gclk_intra_mbAddrA_Cr @ Intra_pred_reg_ctrl.v
|
wire intra_mbAddrA_Cr_ena;
|
wire intra_mbAddrA_Cr_ena;
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reg l_intra_mbAddrA_Cr_ena;
|
reg l_intra_mbAddrA_Cr_ena;
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wire gclk_intra_mbAddrA_Cr;
|
wire gclk_intra_mbAddrA_Cr;
|
wire Is_CrRightMostBlk4x4;
|
wire Is_CrRightMostBlk4x4;
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assign Is_CrRightMostBlk4x4 = (blk4x4_rec_counter == 21 || blk4x4_rec_counter == 23);
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assign Is_CrRightMostBlk4x4 = (blk4x4_rec_counter == 21 || blk4x4_rec_counter == 23);
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assign intra_mbAddrA_Cr_ena = (blk4x4_sum_counter == 3'd3 && (
|
assign intra_mbAddrA_Cr_ena = (blk4x4_sum_counter == 3'd3 && (
|
//Intra4x4
|
//Intra4x4
|
(mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4) ||
|
(mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4) ||
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//Intra16x16 && Inter (including skip MB)
|
//Intra16x16 && Inter (including skip MB)
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(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4 && !NextMB_IsSkip)));
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(mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4 && !NextMB_IsSkip)));
|
always @ (clk or intra_mbAddrA_Cr_ena)
|
always @ (clk or intra_mbAddrA_Cr_ena)
|
if (!clk) l_intra_mbAddrA_Cr_ena <= intra_mbAddrA_Cr_ena;
|
if (!clk) l_intra_mbAddrA_Cr_ena <= intra_mbAddrA_Cr_ena;
|
assign gclk_intra_mbAddrA_Cr = l_intra_mbAddrA_Cr_ena & clk;
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assign gclk_intra_mbAddrA_Cr = l_intra_mbAddrA_Cr_ena & clk;
|
|
|
//4.gclk_intra_mbAddrB @ Intra_pred_reg_ctrl.v
|
//4.gclk_intra_mbAddrB @ Intra_pred_reg_ctrl.v
|
// Control the write of Intra_mbAddrB_reg0 ~ reg 15
|
// Control the write of Intra_mbAddrB_reg0 ~ reg 15
|
wire intra_mbAddrB_ena;
|
wire intra_mbAddrB_ena;
|
reg l_intra_mbAddrB_ena;
|
reg l_intra_mbAddrB_ena;
|
wire gclk_intra_mbAddrB;
|
wire gclk_intra_mbAddrB;
|
assign intra_mbAddrB_ena = (
|
assign intra_mbAddrB_ena = (
|
// Intra4x4
|
// Intra4x4
|
(mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 &&
|
(mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 &&
|
(blk4x4_intra_preload_counter == 1 || blk4x4_sum_counter[2] != 1'b1)) ||
|
(blk4x4_intra_preload_counter == 1 || blk4x4_sum_counter[2] != 1'b1)) ||
|
// Intra16x16
|
// Intra16x16
|
(mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && blk4x4_intra_preload_counter !=0) ||
|
(mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && blk4x4_intra_preload_counter !=0) ||
|
// Intra chroma
|
// Intra chroma
|
(mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && blk4x4_intra_preload_counter !=0));
|
(mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && blk4x4_intra_preload_counter !=0));
|
always @ (clk or intra_mbAddrB_ena)
|
always @ (clk or intra_mbAddrB_ena)
|
if (!clk) l_intra_mbAddrB_ena <= intra_mbAddrB_ena;
|
if (!clk) l_intra_mbAddrB_ena <= intra_mbAddrB_ena;
|
assign gclk_intra_mbAddrB = l_intra_mbAddrB_ena & clk;
|
assign gclk_intra_mbAddrB = l_intra_mbAddrB_ena & clk;
|
|
|
//5.gclk_intra_mbAddrC_luma @ Intra_pred_reg_ctrl.v
|
//5.gclk_intra_mbAddrC_luma @ Intra_pred_reg_ctrl.v
|
//1)For blkIdx=0/1/4/5,Intra_mbAddrC_reg are loaded from Intra_mbAddrB_RAM
|
//1)For blkIdx=0/1/4/5,Intra_mbAddrC_reg are loaded from Intra_mbAddrB_RAM
|
//2)For blkIdx other than 0/1/4/5,Intra_mbAddrC_reg directly obtained from Intra_mbAddrB_reg
|
//2)For blkIdx other than 0/1/4/5,Intra_mbAddrC_reg directly obtained from Intra_mbAddrB_reg
|
wire intra_mbAddrC_luma_ena;
|
wire intra_mbAddrC_luma_ena;
|
reg l_intra_mbAddrC_luma_ena;
|
reg l_intra_mbAddrC_luma_ena;
|
wire gclk_intra_mbAddrC_luma;
|
wire gclk_intra_mbAddrC_luma;
|
assign intra_mbAddrC_luma_ena = (mb_type_general[3:2] == 2'b11 && (Intra4x4_predmode == Intra4x4_Diagonal_Down_Left
|
assign intra_mbAddrC_luma_ena = (mb_type_general[3:2] == 2'b11 && (Intra4x4_predmode == Intra4x4_Diagonal_Down_Left
|
|| Intra4x4_predmode == Intra4x4_Vertical_Left) && blk4x4_intra_preload_counter == 3'b010);
|
|| Intra4x4_predmode == Intra4x4_Vertical_Left) && blk4x4_intra_preload_counter == 3'b010);
|
always @ (clk or intra_mbAddrC_luma_ena)
|
always @ (clk or intra_mbAddrC_luma_ena)
|
if (!clk) l_intra_mbAddrC_luma_ena <= intra_mbAddrC_luma_ena;
|
if (!clk) l_intra_mbAddrC_luma_ena <= intra_mbAddrC_luma_ena;
|
assign gclk_intra_mbAddrC_luma = l_intra_mbAddrC_luma_ena & clk;
|
assign gclk_intra_mbAddrC_luma = l_intra_mbAddrC_luma_ena & clk;
|
|
|
//6.gclk_intra_mbAddrD @ Intra_pred_reg_ctrl.v
|
//6.gclk_intra_mbAddrD @ Intra_pred_reg_ctrl.v
|
//1)For Intra4x4 blkIdx=1/4/5 or Intra16x16 & Chrom plane mode,Intra mbAddrD regs are loaded from
|
//1)For Intra4x4 blkIdx=1/4/5 or Intra16x16 & Chrom plane mode,Intra mbAddrD regs are loaded from
|
// Intra_mbAddrB_RAM.
|
// Intra_mbAddrB_RAM.
|
//2)For blkIdx other than 1/4/5,Intra mbAddrD reg are updated during sum
|
//2)For blkIdx other than 1/4/5,Intra mbAddrD reg are updated during sum
|
wire intra_mbAddrD_ena;
|
wire intra_mbAddrD_ena;
|
reg l_intra_mbAddrD_ena;
|
reg l_intra_mbAddrD_ena;
|
wire gclk_intra_mbAddrD;
|
wire gclk_intra_mbAddrD;
|
assign intra_mbAddrD_ena = (
|
assign intra_mbAddrD_ena = (
|
//1.Update when blkIdx = 15,19,23,from Intra_mbAddrB_RAM
|
//1.Update when blkIdx = 15,19,23,from Intra_mbAddrB_RAM
|
// In reality,sum_counter = 0/1/2/3 are all OK for update,we choose sum_counter = 0 here
|
// In reality,sum_counter = 0/1/2/3 are all OK for update,we choose sum_counter = 0 here
|
(blk4x4_sum_counter == 3'd1 && mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip &&
|
(blk4x4_sum_counter == 3'd1 && mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip &&
|
(blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23)) ||
|
(blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23)) ||
|
(mb_type_general[3:2] == 2'b11 && (
|
(mb_type_general[3:2] == 2'b11 && (
|
//2.For blk4x4 1/4/5 mbAddrD reg update from Intra_mbAddrB_RAM
|
//2.For blk4x4 1/4/5 mbAddrD reg update from Intra_mbAddrB_RAM
|
(blk4x4_intra_preload_counter == 3'b010 &&
|
(blk4x4_intra_preload_counter == 3'b010 &&
|
(Intra4x4_predmode == Intra4x4_Diagonal_Down_Right || Intra4x4_predmode == Intra4x4_Vertical_Right
|
(Intra4x4_predmode == Intra4x4_Diagonal_Down_Right || Intra4x4_predmode == Intra4x4_Vertical_Right
|
|| Intra4x4_predmode == Intra4x4_Horizontal_Down)) ||
|
|| Intra4x4_predmode == Intra4x4_Horizontal_Down)) ||
|
//3.For other blk4x4 mbAddrD reg update from sum output
|
//3.For other blk4x4 mbAddrD reg update from sum output
|
(blk4x4_sum_counter == 3'd3 && (
|
(blk4x4_sum_counter == 3'd3 && (
|
blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 ||
|
blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 ||
|
blk4x4_rec_counter == 2 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 6 ||
|
blk4x4_rec_counter == 2 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 6 ||
|
blk4x4_rec_counter == 8 || blk4x4_rec_counter == 9 || blk4x4_rec_counter == 12)))));
|
blk4x4_rec_counter == 8 || blk4x4_rec_counter == 9 || blk4x4_rec_counter == 12)))));
|
always @ (clk or intra_mbAddrD_ena)
|
always @ (clk or intra_mbAddrD_ena)
|
if (!clk) l_intra_mbAddrD_ena <= intra_mbAddrD_ena;
|
if (!clk) l_intra_mbAddrD_ena <= intra_mbAddrD_ena;
|
assign gclk_intra_mbAddrD = l_intra_mbAddrD_ena & clk;
|
assign gclk_intra_mbAddrD = l_intra_mbAddrD_ena & clk;
|
|
|
//7.gclk_seed @ Intra_pred_reg_ctrl.v
|
//7.gclk_seed @ Intra_pred_reg_ctrl.v
|
wire seed_ena;
|
wire seed_ena;
|
reg l_seed_ena;
|
reg l_seed_ena;
|
wire gclk_seed;
|
wire gclk_seed;
|
//assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ((Intra16x16_predmode == Intra16x16_Plane ||
|
//assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ((Intra16x16_predmode == Intra16x16_Plane ||
|
//Intra_chroma_predmode == Intra_chroma_Plane) && blk4x4_intra_calculate_counter == 3));
|
//Intra_chroma_predmode == Intra_chroma_Plane) && blk4x4_intra_calculate_counter == 3));
|
|
|
assign seed_ena = (blk4x4_intra_precompute_counter == 1 || (
|
assign seed_ena = (blk4x4_intra_precompute_counter == 1 || (
|
(Intra16x16_predmode == Intra16x16_Plane && (
|
(Intra16x16_predmode == Intra16x16_Plane && (
|
((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8) &&
|
((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8) &&
|
blk4x4_intra_calculate_counter == 3'b100) ||
|
blk4x4_intra_calculate_counter == 3'b100) ||
|
((blk4x4_rec_counter == 1 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 9 ||
|
((blk4x4_rec_counter == 1 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 9 ||
|
blk4x4_rec_counter == 11) && blk4x4_intra_calculate_counter == 3'b001))) ||
|
blk4x4_rec_counter == 11) && blk4x4_intra_calculate_counter == 3'b001))) ||
|
(Intra_chroma_predmode == Intra_chroma_Plane && (
|
(Intra_chroma_predmode == Intra_chroma_Plane && (
|
(blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_calculate_counter == 3'b100))));
|
(blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_calculate_counter == 3'b100))));
|
|
|
always @ (clk or seed_ena)
|
always @ (clk or seed_ena)
|
if (!clk) l_seed_ena <= seed_ena;
|
if (!clk) l_seed_ena <= seed_ena;
|
assign gclk_seed = l_seed_ena & clk;
|
assign gclk_seed = l_seed_ena & clk;
|
|
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//Inter pred
|
//Inter pred
|
//-------------------------------------------------
|
//-------------------------------------------------
|
wire Inter_ref_rf_ena;
|
wire Inter_ref_rf_ena;
|
reg l_Inter_ref_rf_ena;
|
reg l_Inter_ref_rf_ena;
|
wire gclk_Inter_ref_rf;
|
wire gclk_Inter_ref_rf;
|
assign Inter_ref_rf_ena = (blk4x4_inter_preload_counter == 0)? 1'b0:1'b1;
|
assign Inter_ref_rf_ena = (blk4x4_inter_preload_counter == 0)? 1'b0:1'b1;
|
always @ (clk or Inter_ref_rf_ena)
|
always @ (clk or Inter_ref_rf_ena)
|
if (!clk) l_Inter_ref_rf_ena <= Inter_ref_rf_ena;
|
if (!clk) l_Inter_ref_rf_ena <= Inter_ref_rf_ena;
|
assign gclk_Inter_ref_rf = l_Inter_ref_rf_ena & clk;
|
assign gclk_Inter_ref_rf = l_Inter_ref_rf_ena & clk;
|
|
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//sum
|
//sum
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//1.gclk_pred_output
|
//1.gclk_pred_output
|
wire pred_output_ena;
|
wire pred_output_ena;
|
reg l_pred_output_ena;
|
reg l_pred_output_ena;
|
wire gclk_pred_output;
|
wire gclk_pred_output;
|
assign pred_output_ena = (blk4x4_intra_calculate_counter != 0 || Inter_blk4x4_pred_output_valid != 0)? 1'b1:1'b0;
|
assign pred_output_ena = (blk4x4_intra_calculate_counter != 0 || Inter_blk4x4_pred_output_valid != 0)? 1'b1:1'b0;
|
always @ (clk or pred_output_ena)
|
always @ (clk or pred_output_ena)
|
if (!clk) l_pred_output_ena <= pred_output_ena;
|
if (!clk) l_pred_output_ena <= pred_output_ena;
|
assign gclk_pred_output = l_pred_output_ena & clk;
|
assign gclk_pred_output = l_pred_output_ena & clk;
|
|
|
//2.gclk_blk4x4_sum
|
//2.gclk_blk4x4_sum
|
wire blk4x4_sum_ena;
|
wire blk4x4_sum_ena;
|
reg l_blk4x4_sum_ena;
|
reg l_blk4x4_sum_ena;
|
wire gclk_blk4x4_sum;
|
wire gclk_blk4x4_sum;
|
assign blk4x4_sum_ena = (blk4x4_sum_counter[2] != 1'b1);
|
assign blk4x4_sum_ena = (blk4x4_sum_counter[2] != 1'b1);
|
always @ (clk or blk4x4_sum_ena)
|
always @ (clk or blk4x4_sum_ena)
|
if (!clk) l_blk4x4_sum_ena <= blk4x4_sum_ena;
|
if (!clk) l_blk4x4_sum_ena <= blk4x4_sum_ena;
|
assign gclk_blk4x4_sum = l_blk4x4_sum_ena & clk;
|
assign gclk_blk4x4_sum = l_blk4x4_sum_ena & clk;
|
|
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//deblocking filter
|
//deblocking filter
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//1.gclk_end_of_MB_DEC
|
//1.gclk_end_of_MB_DEC
|
reg l_end_of_MB_DEC;
|
reg l_end_of_MB_DEC;
|
wire gclk_end_of_MB_DEC;
|
wire gclk_end_of_MB_DEC;
|
always @ (clk or end_of_MB_DEC)
|
always @ (clk or end_of_MB_DEC)
|
if (!clk) l_end_of_MB_DEC <= end_of_MB_DEC;
|
if (!clk) l_end_of_MB_DEC <= end_of_MB_DEC;
|
assign gclk_end_of_MB_DEC = l_end_of_MB_DEC & clk;
|
assign gclk_end_of_MB_DEC = l_end_of_MB_DEC & clk;
|
//2.gclk_DF
|
//2.gclk_DF
|
wire DF_ena;
|
wire DF_ena;
|
reg l_DF_ena;
|
reg l_DF_ena;
|
assign DF_ena = DF_duration | end_of_BS_DEC;
|
assign DF_ena = DF_duration | end_of_BS_DEC;
|
always @ (clk or DF_ena)
|
always @ (clk or DF_ena)
|
if (!clk) l_DF_ena <= DF_ena;
|
if (!clk) l_DF_ena <= DF_ena;
|
assign gclk_DF = l_DF_ena & clk;
|
assign gclk_DF = l_DF_ena & clk;
|
|
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//memory
|
//memory
|
//-------------------------------------------------
|
//-------------------------------------------------
|
//gclk_Intra_mbAddrB_RAM
|
//gclk_Intra_mbAddrB_RAM
|
wire Intra_mbAddrB_RAM_ena;
|
wire Intra_mbAddrB_RAM_ena;
|
reg l_Intra_mbAddrB_RAM_ena;
|
reg l_Intra_mbAddrB_RAM_ena;
|
wire gclk_Intra_mbAddrB_RAM;
|
wire gclk_Intra_mbAddrB_RAM;
|
assign Intra_mbAddrB_RAM_ena = Intra_mbAddrB_RAM_rd | Intra_mbAddrB_RAM_wr;
|
assign Intra_mbAddrB_RAM_ena = Intra_mbAddrB_RAM_rd | Intra_mbAddrB_RAM_wr;
|
always @ (clk or Intra_mbAddrB_RAM_ena)
|
always @ (clk or Intra_mbAddrB_RAM_ena)
|
if (!clk) l_Intra_mbAddrB_RAM_ena <= Intra_mbAddrB_RAM_ena;
|
if (!clk) l_Intra_mbAddrB_RAM_ena <= Intra_mbAddrB_RAM_ena;
|
assign gclk_Intra_mbAddrB_RAM = clk & l_Intra_mbAddrB_RAM_ena;
|
assign gclk_Intra_mbAddrB_RAM = clk & l_Intra_mbAddrB_RAM_ena;
|
|
|
//gclk_rec_DF_RAM0
|
//gclk_rec_DF_RAM0
|
reg l_rec_DF_RAM0_ena;
|
reg l_rec_DF_RAM0_ena;
|
wire gclk_rec_DF_RAM0;
|
wire gclk_rec_DF_RAM0;
|
always @ (clk or rec_DF_RAM0_cs_n)
|
always @ (clk or rec_DF_RAM0_cs_n)
|
if (!clk) l_rec_DF_RAM0_ena <= !rec_DF_RAM0_cs_n;
|
if (!clk) l_rec_DF_RAM0_ena <= !rec_DF_RAM0_cs_n;
|
assign gclk_rec_DF_RAM0 = clk & l_rec_DF_RAM0_ena;
|
assign gclk_rec_DF_RAM0 = clk & l_rec_DF_RAM0_ena;
|
|
|
//gclk_rec_DF_RAM1
|
//gclk_rec_DF_RAM1
|
reg l_rec_DF_RAM1_ena;
|
reg l_rec_DF_RAM1_ena;
|
wire gclk_rec_DF_RAM1;
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wire gclk_rec_DF_RAM1;
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always @ (clk or rec_DF_RAM1_cs_n)
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always @ (clk or rec_DF_RAM1_cs_n)
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if (!clk) l_rec_DF_RAM1_ena <= !rec_DF_RAM1_cs_n;
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if (!clk) l_rec_DF_RAM1_ena <= !rec_DF_RAM1_cs_n;
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assign gclk_rec_DF_RAM1 = clk & l_rec_DF_RAM1_ena;
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assign gclk_rec_DF_RAM1 = clk & l_rec_DF_RAM1_ena;
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//gclk_DF_mbAddrA_RF
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//gclk_DF_mbAddrA_RF
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wire DF_mbAddrA_RF_ena;
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wire DF_mbAddrA_RF_ena;
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reg l_DF_mbAddrA_RF_ena;
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reg l_DF_mbAddrA_RF_ena;
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wire gclk_DF_mbAddrA_RF;
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wire gclk_DF_mbAddrA_RF;
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assign DF_mbAddrA_RF_ena = DF_mbAddrA_RF_rd | DF_mbAddrA_RF_wr;
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assign DF_mbAddrA_RF_ena = DF_mbAddrA_RF_rd | DF_mbAddrA_RF_wr;
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always @ (clk or DF_mbAddrA_RF_ena)
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always @ (clk or DF_mbAddrA_RF_ena)
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if (!clk) l_DF_mbAddrA_RF_ena <= DF_mbAddrA_RF_ena;
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if (!clk) l_DF_mbAddrA_RF_ena <= DF_mbAddrA_RF_ena;
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assign gclk_DF_mbAddrA_RF = clk & l_DF_mbAddrA_RF_ena;
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assign gclk_DF_mbAddrA_RF = clk & l_DF_mbAddrA_RF_ena;
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//gclk_DF_mbAddrB_RAM
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//gclk_DF_mbAddrB_RAM
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wire DF_mbAddrB_RAM_ena;
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wire DF_mbAddrB_RAM_ena;
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reg l_DF_mbAddrB_RAM_ena;
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reg l_DF_mbAddrB_RAM_ena;
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wire gclk_DF_mbAddrB_RAM;
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wire gclk_DF_mbAddrB_RAM;
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assign DF_mbAddrB_RAM_ena = DF_mbAddrB_RAM_rd | DF_mbAddrB_RAM_wr;
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assign DF_mbAddrB_RAM_ena = DF_mbAddrB_RAM_rd | DF_mbAddrB_RAM_wr;
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always @ (clk or DF_mbAddrB_RAM_ena)
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always @ (clk or DF_mbAddrB_RAM_ena)
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if (!clk) l_DF_mbAddrB_RAM_ena <= DF_mbAddrB_RAM_ena;
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if (!clk) l_DF_mbAddrB_RAM_ena <= DF_mbAddrB_RAM_ena;
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assign gclk_DF_mbAddrB_RAM = clk & l_DF_mbAddrB_RAM_ena;
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assign gclk_DF_mbAddrB_RAM = clk & l_DF_mbAddrB_RAM_ena;
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endmodule
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endmodule
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