URL
https://opencores.org/ocsvn/onewire/onewire/trunk
[/] [onewire/] [trunk/] [HDL/] [ds1820_mstr_tb.vhd] - Diff between revs 2 and 4
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 4 |
| Line 108... |
Line 108... |
signal tempidx : unsigned(4 downto 0); --index of the current temp sensor
|
signal tempidx : unsigned(4 downto 0); --index of the current temp sensor
|
signal tempstb : std_logic; --strobe to indicate an updated temp sensor value
|
signal tempstb : std_logic; --strobe to indicate an updated temp sensor value
|
signal owin : std_logic; --one wire input to dut
|
signal owin : std_logic; --one wire input to dut
|
signal owout : std_logic; --one wire output from dut
|
signal owout : std_logic; --one wire output from dut
|
signal dio : std_logic; --one wire bus
|
signal dio : std_logic; --one wire bus
|
|
signal pio : std_logic; --switch of ds2405
|
|
|
begin
|
begin
|
|
|
-------------------------------------
|
-------------------------------------
|
-- global timing signals ---
|
-- global timing signals ---
|
| Line 304... |
Line 305... |
|
|
--simulated temperature sensor
|
--simulated temperature sensor
|
u_ds18b20_3 : entity work.ds18b20_sim(sim)
|
u_ds18b20_3 : entity work.ds18b20_sim(sim)
|
generic map (
|
generic map (
|
timing => "min",
|
timing => "min",
|
devid => x"0083726dab32bf28"
|
devid => x"0083726d2b32bf28"
|
)
|
)
|
port map (
|
port map (
|
--dio => dio3,
|
--dio => dio3,
|
pwrin => '1',
|
pwrin => '1',
|
dio => dio,
|
dio => dio,
|
tempin => 57.25
|
tempin => 57.25
|
);
|
);
|
|
u_ds18b20_4 : entity work.ds18b20_sim(sim)
|
|
generic map (
|
|
timing => "min",
|
|
devid => x"0083726d3b32bf28"
|
|
)
|
|
port map (
|
|
--dio => dio3,
|
|
pwrin => '1',
|
|
dio => dio,
|
|
tempin => 57.25
|
|
);
|
|
|
|
--simulated addressable switch
|
|
u_ds2405 : entity work.ds2405_sim(sim)
|
|
generic map (
|
|
timing => "min",
|
|
devid => x"0034756483522105"
|
|
)
|
|
port map (
|
|
--dio => dio3,
|
|
pio => pio,
|
|
dio => dio
|
|
);
|
|
pio <= 'H';
|
|
|
end sim;
|
end sim;
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.