| Line 50... |
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<col width=103 style='mso-width-source:userset;mso-width-alt:3766;width:77pt'>
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<col width=103 style='mso-width-source:userset;mso-width-alt:3766;width:77pt'>
|
<col class=xl67 width=61 style='mso-width-source:userset;mso-width-alt:2230;
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<col class=xl67 width=61 style='mso-width-source:userset;mso-width-alt:2230;
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width:46pt'>
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width:46pt'>
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<col class=xl68 width=893 style='mso-width-source:userset;mso-width-alt:32658;
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<col class=xl68 width=893 style='mso-width-source:userset;mso-width-alt:32658;
|
width:670pt'>
|
width:670pt'>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=35 style='height:26.25pt'>
|
<td height=20 width=185 style='height:15.0pt;width:139pt'></td>
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<td height=35 width=185 style='height:26.25pt;width:139pt'></td>
|
<td width=103 style='width:77pt'></td>
|
<td width=103 style='width:77pt'></td>
|
<td class=xl106 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
|
<td class=xl107 colspan=2 width=954 style='mso-ignore:colspan;width:716pt'>Open8
|
CPU Core Generics</td>
|
CPU Core Generics</td>
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</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=20 style='height:15.0pt'>
|
<td height=20 colspan=2 style='height:15.0pt;mso-ignore:colspan'></td>
|
<td height=20 colspan=2 style='height:15.0pt;mso-ignore:colspan'></td>
|
<td class=xl67></td>
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<td class=xl67></td>
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| Line 96... |
Line 96... |
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
false, the RSP instruction will reset the stack pointer to
|
false, the RSP instruction will reset the stack pointer to
|
"Stack_Start_Addr" by default. If true, the RSP instruction will
|
"Stack_Start_Addr" by default. If true, the RSP instruction will
|
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
|
either allow the stack pointer to be loaded from R1:R0 or copied to R1:R0
|
depending on the status of the specified ALU flag bit.</td>
|
depending on the status of the PSR_GP4 flag.</td>
|
</tr>
|
|
<tr height=80 style='height:60.0pt'>
|
|
<td height=80 class=xl76 style='height:60.0pt;border-top:none'>Stack_Xfer_Flag</td>
|
|
<td class=xl76 style='border-top:none;border-left:none'>Integer 0-7</td>
|
|
<td class=xl103 style='border-top:none;border-left:none'>PSR_GP4</td>
|
|
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Specifies
|
|
which processor flag controls the behavior of RSP when
|
|
'Allow_Stack_Address_move' is true. If the specified bit is clear ('0'), the
|
|
RSP instruction will transfer the stack pointer to R1:R0 (SP -> R1:R0),
|
|
otherwise, if it is true ('1'), the RSP instruction will set the stack
|
|
pointer from R1:R0 ( R1:R0 -> SP ). Any of the 8 CPU flags may be
|
|
specified, but the intent was to use FL_GP[1-4], as these are purely under
|
|
software control and are not otherwise modified by the ALU.</td>
|
|
</tr>
|
</tr>
|
<tr height=80 style='height:60.0pt'>
|
<tr height=80 style='height:60.0pt'>
|
<td height=80 class=xl73 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
|
<td height=80 class=xl108 style='height:60.0pt;border-top:none'>Enable_Auto_Increment</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
true, indexed instructions such as LDX, LDO, STX, STO will automatically
|
true, indexed instructions such as LDX, LDO, STX, STO will automatically
|
increment if an odd register is specified. The effect is similar to a normal
|
increment if an odd register is specified. The effect is similar to a normal
|
indexed instruction followed by an UPP instruction on the same register pair.
|
indexed instruction followed by an UPP instruction on the same register pair.
|
For example, LDX R5 (or LDX R4++) will result in R0 getting the data stored
|
For example, LDX R5 (or LDX R4++) will result in R0 getting the data stored
|
at the address specified by R5:R4. Afterwards, the register pair R5:R4 will
|
at the address specified by R5:R4. Afterwards, the register pair R5:R4 will
|
be incremented by 1. If false, specifying either register in a register pair
|
be incremented by 1. If false, specifying either register in a register pair
|
will result in normal behavior.</td>
|
will result in normal behavior.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=40 class=xl76 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
|
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>BRK_Implements_WAI</td>
|
<td class=xl76 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl103 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
true, the BRK instruction will cause the processor to halt as if an INT
|
true, the BRK instruction will cause the processor to halt as if an INT
|
instruction was executed, but without triggering an interrupt. This is useful
|
instruction was executed, but without triggering an interrupt. This is useful
|
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
|
for pausing the CPU until an interrupt occurs. If false, the BRK instruction
|
simply causes the CPU to execute 5 NOP cycles.</td>
|
simply causes the CPU to execute 5 NOP cycles.</td>
|
</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=20 style='height:15.0pt'>
|
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Enable_NMI</td>
|
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Enable_NMI</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl74 style='border-top:none;border-left:none'>TRUE</td>
|
<td class=xl109 style='border-top:none;border-left:none'>TRUE</td>
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Forces
|
bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
|
bit 0 of the Interrupt Mask to 1, causing Interrupt 0 to be non-maskable.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=40 class=xl76 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
|
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Sequential_Interrupts</td>
|
<td class=xl76 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl103 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Prohibits
|
interrupts from initiating an ISR if the I-bit is set, making ISRs
|
interrupts from initiating an ISR if the I-bit is set, making ISRs
|
sequential. This potentially blocks interrupt priority by allowing a lower
|
sequential. This potentially blocks interrupt priority by allowing a lower
|
level interrupt to block a higher level interrupt. This can be fixed by
|
level interrupt to block a higher level interrupt. This can be fixed by
|
clearing the I-bit in interruptable ISRs.</td>
|
clearing the I-bit in interruptable ISRs.</td>
|
</tr>
|
</tr>
|
<tr height=40 style='height:30.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
|
<td height=40 class=xl108 style='height:30.0pt;border-top:none'>RTI_Ignores_GP_Flags</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit,
|
set, preserves the general purpose flags GP_PSR4 to GP_PSR7 on ISR exit,
|
allowing them to be persistently set by interrupts. The lower four flag bits
|
allowing them to be persistently set by interrupts. The lower four flag bits
|
are always restored.</td>
|
are always restored.</td>
|
</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=40 style='height:30.0pt'>
|
<td height=20 class=xl76 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
|
<td height=40 class=xl73 style='height:30.0pt;border-top:none'>Supervisor_Mode</td>
|
<td class=xl76 style='border-top:none;border-left:none'>8-bit Data</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Boolean</td>
|
<td class=xl103 style='border-top:none;border-left:none'>x"FF"</td>
|
<td class=xl74 style='border-top:none;border-left:none'>FALSE</td>
|
<td class=xl78 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>If
|
|
set to true, enables restrictions on RSP, CLP/STP, and SMSK where they only
|
|
can alter internal registers if the I bit is set. Also initializes the CPU to
|
|
start with the I-bit set. If set to false, there are no restrictions on these
|
|
instructions.</td>
|
|
</tr>
|
|
<tr height=20 style='height:15.0pt'>
|
|
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Unsigned_Index_Offsets</td>
|
|
<td class=xl108 style='border-top:none;border-left:none'>Boolean</td>
|
|
<td class=xl109 style='border-top:none;border-left:none'>FALSE</td>
|
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Determines
|
|
whether the offset calculation for LDO/STO is signed or unsigned. Default
|
|
behavior is signed.</td>
|
|
</tr>
|
|
<tr height=20 style='height:15.0pt'>
|
|
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Default_Interrupt_Mask</td>
|
|
<td class=xl73 style='border-top:none;border-left:none'>8-bit Data</td>
|
|
<td class=xl74 style='border-top:none;border-left:none'>x"FF"</td>
|
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Sets
|
the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td>
|
the initial interrupt mask (note that bit 0 is ignored, as this is the NMI)</td>
|
</tr>
|
</tr>
|
<tr height=20 style='height:15.0pt'>
|
<tr height=20 style='height:15.0pt'>
|
<td height=20 class=xl73 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
|
<td height=20 class=xl108 style='height:15.0pt;border-top:none'>Clock_Frequency</td>
|
<td class=xl73 style='border-top:none;border-left:none'>Real</td>
|
<td class=xl108 style='border-top:none;border-left:none'>Real</td>
|
<td class=xl74 style='border-top:none;border-left:none'>-</td>
|
<td class=xl109 style='border-top:none;border-left:none'>-</td>
|
<td class=xl75 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
|
<td class=xl110 width=893 style='border-top:none;border-left:none;width:670pt'>Clock
|
frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
|
frequency in Hz of the CPU clock. Used to configure the 1Mhz/1uSec tick pulse</td>
|
</tr>
|
</tr>
|
<![if supportMisalignedColumns]>
|
<![if supportMisalignedColumns]>
|
<tr height=0 style='display:none'>
|
<tr height=0 style='display:none'>
|
<td width=185 style='width:139pt'></td>
|
<td width=185 style='width:139pt'></td>
|
