OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Diff between revs 270 and 313

Show entire file | Details | Blame | View Log

Rev 270 Rev 313
Line 108... Line 108...
 
 
  -- Component declaration
  -- Component declaration
  --  (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
  --  (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
  component o8_cpu is
  component o8_cpu is
  generic(
  generic(
    Program_Start_Addr       : ADDRESS_TYPE := x"8000";
    Program_Start_Addr       : ADDRESS_TYPE := x"8000"; -- Initial PC location
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0";
    ISR_Start_Addr           : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF";
    Stack_Start_Addr         : ADDRESS_TYPE := x"03FF"; -- Top of Stack
    Allow_Stack_Address_Move : boolean      := false;
    Allow_Stack_Address_Move : boolean      := false;   -- Use Normal v8 RSP
    Enable_Auto_Increment    : boolean      := false;
    Enable_Auto_Increment    : boolean      := false;   -- Modify indexed instr
    BRK_Implements_WAI       : boolean      := false;
    BRK_Implements_WAI       : boolean      := false;   -- BRK -> Wait for Int
    Enable_NMI               : boolean      := true;
    Enable_NMI               : boolean      := false;   -- Force INTR0 enabled
    RTI_Ignores_GP_Flags     : boolean      := false;
    Sequential_Interrupts    : boolean      := false;   -- Interruptable ISRs
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";
    RTI_Ignores_GP_Flags     : boolean      := false;   -- RTI sets all flags
    Clock_Frequency          : real
    Supervisor_Mode          : boolean      := false;   -- I bit is restricted
 
    Unsigned_Index_Offsets   : boolean      := false;   -- Offsets are signed
 
    Rotate_Ignores_Carry     : boolean      := false;   -- Rotate thru Carry
 
    Default_Interrupt_Mask   : DATA_TYPE    := x"FF";   -- Enable all Ints
 
    Clock_Frequency          : real                     -- Clock Frequency
  );
  );
  port(
  port(
    Clock                    : in  std_logic;
    Clock                    : in  std_logic;
    PLL_Locked               : in  std_logic;
    PLL_Locked               : in  std_logic;
    Halt_Req                 : in  std_logic := '0';
    Halt_Req                 : in  std_logic := '0';

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.