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[/] [open8_urisc/] [trunk/] [VHDL/] [adc128s022.vhd] - Diff between revs 315 and 317
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| Rev 315 |
Rev 317 |
| Line 44... |
Line 44... |
);
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);
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port(
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port(
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Reinit : in std_logic;
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Reinit : in std_logic := '0'; -- Optional sync reset
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--
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--
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RAW_Channel : out std_logic_vector(2 downto 0);
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RAW_Channel : out std_logic_vector(2 downto 0);
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RAW_Data : out std_logic_vector(15 downto 0);
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RAW_Data : out std_logic_vector(15 downto 0);
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RAW_Valid : out std_logic;
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RAW_Valid : out std_logic;
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--
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--
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