| Line 154... |
Line 154... |
-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 07/19/06 Design Start
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-- Seth Henry 03/13/15 Added "Almost Equal" instruction
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-- Seth Henry 03/13/15 Added "Almost Equal" instruction
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-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
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-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
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-- Seth Henry 04/10/20 Comment and code cleanup
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-- Seth Henry 04/10/20 Comment and code cleanup
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 05/18/20 Added write qualification input
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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| Line 170... |
Line 171... |
generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '0';
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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| Line 243... |
Line 245... |
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constant User_Addr : std_logic_vector(15 downto 5):=
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constant User_Addr : std_logic_vector(15 downto 5):=
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Address(15 downto 5);
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Address(15 downto 5);
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alias Comp_Addr is Open8_Bus.Address(15 downto 5);
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alias Comp_Addr is Open8_Bus.Address(15 downto 5);
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signal Reg_Addr : std_logic_vector(4 downto 0) :=
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(others => '0');
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := (others => '0');
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alias Reg_Sel_d is Open8_Bus.Address(4 downto 0);
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signal Rd_En : std_logic := '0';
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signal Reg_Sel_q : std_logic_vector(4 downto 0) := "00000";
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signal Wr_En_d : std_logic := '0';
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signal Wr_En_q : std_logic := '0';
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alias Wr_Data_d is Open8_Bus.Wr_Data;
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
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type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
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signal regfile : REG_ARRAY := (
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signal regfile : REG_ARRAY := (
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x"0000",x"0000",x"0000",x"0000",
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x"0000",x"0000",x"0000",x"0000",
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x"0000",x"0000",x"0000",x"0000");
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x"0000",x"0000",x"0000",x"0000");
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(others => '0');
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(others => '0');
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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-- Sign-extend the base operands to created operands for signed math
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-- Sign-extend the base operands to created operands for signed math
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S_Operand_1 <= signed(Operand_1(15) & Operand_1);
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S_Operand_1 <= signed(Operand_1(15) & Operand_1);
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S_Operand_2 <= signed(Operand_2(15) & Operand_2);
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S_Operand_2 <= signed(Operand_2(15) & Operand_2);
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Line 401... |
ALU_proc: process( Clock, Reset )
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ALU_proc: process( Clock, Reset )
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variable Reg_Sel : integer;
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variable Reg_Sel : integer;
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variable Oper_Sel : integer;
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variable Oper_Sel : integer;
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Wr_En <= '0';
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Reg_Sel_q <= (others => '0');
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Wr_Data_q <= (others => '0');
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Wr_En_q <= '0';
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Rd_En <= '0';
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Wr_Data_q <= x"00";
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Rd_En_q <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Reg_Addr <= (others => '0');
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Opcode <= (others => '0');
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Opcode <= (others => '0');
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Operand_Sel <= (others => '0');
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Operand_Sel <= (others => '0');
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Tolerance <= (others => '0');
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Tolerance <= (others => '0');
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Start <= '0';
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Start <= '0';
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Busy_q <= '0';
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Busy_q <= '0';
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| Line 433... |
Line 440... |
count <= DIV_WIDTH;
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count <= DIV_WIDTH;
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IDIV_Busy <= '0';
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IDIV_Busy <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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-- For convenience, convert these to integers and assign them to
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-- For convenience, convert these to integers and assign them to
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-- variables
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-- variables
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Reg_Sel := conv_integer(Reg_Addr(3 downto 1));
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Reg_Sel := conv_integer(Reg_Sel_q(3 downto 1));
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Oper_Sel := conv_integer(Operand_Sel);
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Oper_Sel := conv_integer(Operand_Sel);
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_q <= Wr_En_d;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_Data_q <= Wr_Data_d;
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Reg_Addr <= Open8_Bus.Address(4 downto 0);
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Reg_Sel_q <= Reg_Sel_d;
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Start <= '0';
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Start <= '0';
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if( Wr_En = '1' )then
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if( Wr_En_q = '1' )then
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case( Reg_Addr )is
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case( Reg_Sel_q )is
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-- Even addresses go to the lower byte of the register
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-- Even addresses go to the lower byte of the register
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when "00000" | "00010" | "00100" | "00110" |
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when "00000" | "00010" | "00100" | "00110" |
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"01000" | "01010" | "01100" | "01110" =>
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"01000" | "01010" | "01100" | "01110" =>
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regfile(Reg_Sel)(7 downto 0) <= Wr_Data_q;
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regfile(Reg_Sel)(7 downto 0) <= Wr_Data_q;
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Line 477... |
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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Rd_En_q <= Rd_En_d;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En_q = '1' )then
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case( Reg_Sel_q )is
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if( Rd_En = '1' )then
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case( Reg_Addr )is
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when "00000" | "00010" | "00100" | "00110" |
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when "00000" | "00010" | "00100" | "00110" |
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"01000" | "01010" | "01100" | "01110" =>
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"01000" | "01010" | "01100" | "01110" =>
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Rd_Data <= regfile(Reg_Sel)(7 downto 0);
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Rd_Data <= regfile(Reg_Sel)(7 downto 0);
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when "00001" | "00011" | "00101" | "00111" |
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when "00001" | "00011" | "00101" | "00111" |
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"01001" | "01011" | "01101" | "01111" =>
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"01001" | "01011" | "01101" | "01111" =>
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