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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Diff between revs 314 and 316

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Rev 314 Rev 316
Line 277... Line 277...
--                           alters the ROR and ROL instructions to behave more
--                           alters the ROR and ROL instructions to behave more
--                           like expected by not rotating through the C flag
--                           like expected by not rotating through the C flag
-- Seth Henry      07/12/22 Fixed a long-standing bug in the SBC instruction
-- Seth Henry      07/12/22 Fixed a long-standing bug in the SBC instruction
--                           where the 2's complement inversion wasn't adding
--                           where the 2's complement inversion wasn't adding
--                           the additional 1, causing off by 1 errors
--                           the additional 1, causing off by 1 errors
 
-- Seth Henry      05/18/23 Removed reset signal from address offset pipeline
 
--                           registers and cleaned up comments. Also removed
 
--                           superfluous constant definitions, as they can't
 
--                           be realistically altered.
 
 
library ieee;
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_arith.all;
Line 319... Line 323...
);
);
end entity;
end entity;
 
 
architecture behave of o8_cpu is
architecture behave of o8_cpu is
 
 
 
  -- The CPU uses the PLL_Locked signal to create an internal reset pulse
  signal Reset_q             : std_logic := Reset_Level;
  signal Reset_q             : std_logic := Reset_Level;
  signal Reset               : std_logic := Reset_Level;
  signal Reset               : std_logic := Reset_Level;
 
 
 
  -- Utility 1uS counter signals & constants. Note that the correct clock
 
  --  frequency is required in Hz. Note that some clock frequencies will not
 
  --  divide cleanly, producing a slightly fast/slow uSec tick signal
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
  constant USEC_VAL          : integer := integer(Clock_Frequency / 1000000.0);
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
  constant USEC_WDT          : integer := ceil_log2(USEC_VAL - 1);
  constant USEC_DLY          : std_logic_vector :=
  constant USEC_DLY          : std_logic_vector :=
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
                                conv_std_logic_vector(USEC_VAL - 1, USEC_WDT);
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
  signal uSec_Cntr           : std_logic_vector( USEC_WDT - 1 downto 0 );
Line 538... Line 546...
  signal Wait_for_ISR        : std_logic := '0';
  signal Wait_for_ISR        : std_logic := '0';
 
 
  alias  ISR_Addr_Base       is ISR_Start_Addr(15 downto 4);
  alias  ISR_Addr_Base       is ISR_Start_Addr(15 downto 4);
  signal ISR_Addr_Offset     : std_logic_vector(3 downto 0) := x"0";
  signal ISR_Addr_Offset     : std_logic_vector(3 downto 0) := x"0";
 
 
  constant INT_VECTOR_0      : std_logic_vector(3 downto 0) := x"0";
 
  constant INT_VECTOR_1      : std_logic_vector(3 downto 0) := x"2";
 
  constant INT_VECTOR_2      : std_logic_vector(3 downto 0) := x"4";
 
  constant INT_VECTOR_3      : std_logic_vector(3 downto 0) := x"6";
 
  constant INT_VECTOR_4      : std_logic_vector(3 downto 0) := x"8";
 
  constant INT_VECTOR_5      : std_logic_vector(3 downto 0) := x"A";
 
  constant INT_VECTOR_6      : std_logic_vector(3 downto 0) := x"C";
 
  constant INT_VECTOR_7      : std_logic_vector(3 downto 0) := x"E";
 
 
 
  signal IDX_Offset_SX       : std_logic := '0';
  signal IDX_Offset_SX       : std_logic := '0';
 
 
  signal IDX_Offset          : ADDRESS_TYPE := x"0000";
  signal IDX_Offset          : ADDRESS_TYPE := x"0000";
 
 
  signal IDX_Sel_l           : std_logic_vector(2 downto 0) := "000";
  signal IDX_Sel_l           : std_logic_vector(2 downto 0) := "000";
Line 1260... Line 1259...
      if( Enable_NMI )then
      if( Enable_NMI )then
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
        Int_Mask             <= Default_Interrupt_Mask(7 downto 1) & '1';
      else
      else
        Int_Mask             <= Default_Interrupt_Mask;
        Int_Mask             <= Default_Interrupt_Mask;
      end if;
      end if;
      ISR_Addr_Offset        <= INT_VECTOR_0;
      ISR_Addr_Offset        <= x"0";
 
 
      for i in 0 to 7 loop
      for i in 0 to 7 loop
        Regfile(i)           <= x"00";
        Regfile(i)           <= x"00";
      end loop;
      end loop;
      Flags                  <= x"00";
      Flags                  <= x"00";
Line 1276... Line 1275...
 
 
    elsif( rising_edge(Clock) )then
    elsif( rising_edge(Clock) )then
 
 
      CPU_State              <= CPU_Next_State;
      CPU_State              <= CPU_Next_State;
 
 
 
-------------------------------------------------------------------------------
-- Register the halt request and acknowledge lines
-- Register the halt request and acknowledge lines
 
-------------------------------------------------------------------------------
 
 
      CPU_Halt_Req           <= Halt_Req;
      CPU_Halt_Req           <= Halt_Req;
      Halt_Ack               <= CPU_Halt_Ack;
      Halt_Ack               <= CPU_Halt_Ack;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Line 1457... Line 1458...
        Wait_for_ISR         <= '0';
        Wait_for_ISR         <= '0';
      end if;
      end if;
 
 
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
      if( Wait_for_FSM = '0' and Wait_for_ISR = '0' )then
        if(    Pending(0) = '1' )then
        if(    Pending(0) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_0;
          ISR_Addr_Offset    <= x"0";
          Pending(0)         <= '0';
          Pending(0)         <= '0';
        elsif( Pending(1) = '1' )then
        elsif( Pending(1) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_1;
          ISR_Addr_Offset    <= x"2";
          Pending(1)         <= '0';
          Pending(1)         <= '0';
        elsif( Pending(2) = '1' )then
        elsif( Pending(2) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_2;
          ISR_Addr_Offset    <= x"4";
          Pending(2)         <= '0';
          Pending(2)         <= '0';
        elsif( Pending(3) = '1' )then
        elsif( Pending(3) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_3;
          ISR_Addr_Offset    <= x"6";
          Pending(3)         <= '0';
          Pending(3)         <= '0';
        elsif( Pending(4) = '1' )then
        elsif( Pending(4) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_4;
          ISR_Addr_Offset    <= x"8";
          Pending(4)         <= '0';
          Pending(4)         <= '0';
        elsif( Pending(5) = '1' )then
        elsif( Pending(5) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_5;
          ISR_Addr_Offset    <= x"A";
          Pending(5)         <= '0';
          Pending(5)         <= '0';
        elsif( Pending(6) = '1' )then
        elsif( Pending(6) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_6;
          ISR_Addr_Offset    <= x"C";
          Pending(6)         <= '0';
          Pending(6)         <= '0';
        elsif( Pending(7) = '1' )then
        elsif( Pending(7) = '1' )then
          ISR_Addr_Offset    <= INT_VECTOR_7;
          ISR_Addr_Offset    <= x"E";
          Pending(7)         <= '0';
          Pending(7)         <= '0';
        end if;
        end if;
        Wait_for_FSM         <= or_reduce(Pending);
        Wait_for_FSM         <= or_reduce(Pending);
      end if;
      end if;
 
 

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