URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_de0_nano_adc_if.vhd] - Diff between revs 315 and 317
Show entire file |
Details |
Blame |
View Log
| Rev 315 |
Rev 317 |
| Line 81... |
Line 81... |
|
|
alias Clock is Open8_Bus.Clock;
|
alias Clock is Open8_Bus.Clock;
|
alias Reset is Open8_Bus.Reset;
|
alias Reset is Open8_Bus.Reset;
|
alias uSec_Tick is Open8_Bus.uSec_Tick;
|
alias uSec_Tick is Open8_Bus.uSec_Tick;
|
|
|
signal Reinit : std_logic := '0';
|
|
|
|
signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
|
signal RAW_Channel : std_logic_vector(2 downto 0) := (others => '0');
|
signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
|
signal RAW_Data : std_logic_vector(15 downto 0) := (others => '0');
|
signal RAW_Valid : std_logic := '0';
|
signal RAW_Valid : std_logic := '0';
|
|
|
signal AVG_Busy : std_logic := '0';
|
signal AVG_Busy : std_logic := '0';
|
| Line 125... |
Line 123... |
)
|
)
|
port map(
|
port map(
|
Clock => Clock,
|
Clock => Clock,
|
Reset => Reset,
|
Reset => Reset,
|
--
|
--
|
Reinit => Reinit,
|
|
--
|
|
RAW_Channel => RAW_Channel,
|
RAW_Channel => RAW_Channel,
|
RAW_Data => RAW_Data,
|
RAW_Data => RAW_Data,
|
RAW_Valid => RAW_Valid,
|
RAW_Valid => RAW_Valid,
|
--
|
--
|
Busy_In => AVG_Busy,
|
Busy_In => AVG_Busy,
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.