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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_register_wide.vhd] - Diff between revs 279 and 297

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Rev 279 Rev 297
Line 24... Line 24...
-- VHDL Units :  o8_register_wide
-- VHDL Units :  o8_register_wide
-- Description:  Provides a single addressible 16-bit output register
-- Description:  Provides a single addressible 16-bit output register
--
--
-- Register Map:
-- Register Map:
-- Offset  Bitfield Description                        Read/Write
-- Offset  Bitfield Description                        Read/Write
--   0x00  AAAAAAAA Registered Outputs                    (RW)
--   0x00  AAAAAAAA Registered Output 0                   (RW)
 
--   0x01  AAAAAAAA Registered Output 1                   (RW)
 
--   0x02  AAAAAAAA Registered Output 2                   (RW)
 
--   0x03  AAAAAAAA Registered Output 3                   (RW)
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      05/24/20 Design copied and modified from o8_register
-- Seth Henry      05/24/20 Design copied and modified from o8_register

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