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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sys_timer_ii.vhd] - Diff between revs 229 and 240

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Rev 229 Rev 240
Line 29... Line 29... 
-- Offset  Bitfield Description                        Read/Write
 
-- Offset  Bitfield Description                        Read/Write
 
--   0x00  AAAAAAAA Req Interval Byte 0                   (RW)
 
--   0x00  AAAAAAAA Req Interval Byte 0                   (RW)
 
--   0x01  AAAAAAAA Req Interval Byte 1                   (RW)
 
--   0x01  AAAAAAAA Req Interval Byte 1                   (RW)
 
--   0x02  AAAAAAAA Req Interval Byte 2                   (RW)
 
--   0x02  AAAAAAAA Req Interval Byte 2                   (RW)
 
--   0x03  BA------ Control/Status Register               (RW)
 
--   0x03  BA------ Control/Status Register               (RW)
 
--                   A: Update timer (WR) or Update pending (RD)
 
--                   A: Update timer (WR) or pending (RD) (RW)
 
--                   B: Output Enable
 
--                   B: Output Enable
 
--
 
--
 
-- Notes      :  Setting the output to 0x000000 will disable the timer
 
-- Notes      :  Setting the output to 0x000000 will disable the timer
 
--            :  Update pending is true if bit A is 1, otherwise false
 
--            :  Update pending is true if bit A is 1, otherwise false
 
--
 
--

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