-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
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-- Copyright (c)2006, 2016, 2019, 2020 Jeremy Seth Henry
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-- All rights reserved.
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-- All rights reserved.
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--
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--
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-- Redistribution and use in source and binary forms, with or without
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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-- * Redistributions of source code must retain the above copyright
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- notice, this list of conditions and the following disclaimer.
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-- * Redistributions in binary form must reproduce the above copyright
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-- * Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution,
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-- documentation and/or other materials provided with the distribution,
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-- where applicable (as part of a user interface, debugging port, etc.)
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-- where applicable (as part of a user interface, debugging port, etc.)
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_sys_timer
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-- VHDL Units : o8_sys_timer
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-- Description: Provides an 8-bit microsecond resolution timer for generating
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-- Description: Provides an 8-bit microsecond resolution timer for generating
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-- : periodic interrupts for the Open8 CPU.
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-- : periodic interrupts for the Open8 CPU.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Req Interval Byte 0 (RW)
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-- 0x00 AAAAAAAA Req Interval Byte 0 (RW)
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-- 0x01 AAAAAAAA Req Interval Byte 1 (RW)
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-- 0x01 AAAAAAAA Req Interval Byte 1 (RW)
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-- 0x02 AAAAAAAA Req Interval Byte 2 (RW)
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-- 0x02 AAAAAAAA Req Interval Byte 2 (RW)
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-- 0x03 BA------ Control/Status Register (RW)
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-- 0x03 BA------ Control/Status Register (RW)
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-- A: Update timer (WR) or Update pending (RD)
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-- A: Update timer (WR) or pending (RD) (RW)
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-- B: Output Enable
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-- B: Output Enable
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--
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--
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-- Notes : Setting the output to 0x000000 will disable the timer
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-- Notes : Setting the output to 0x000000 will disable the timer
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-- : Update pending is true if bit A is 1, otherwise false
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-- : Update pending is true if bit A is 1, otherwise false
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 07/28/11 Design Start
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 12/19/19 Renamed Tmr_Out to Interrupt
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- interval write.
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-- interval write.
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/17/20 Altered interval to be a 24-bit counter
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-- Seth Henry 04/17/20 Altered interval to be a 24-bit counter
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_misc.all;
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use ieee.std_logic_misc.all;
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library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_sys_timer_ii is
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entity o8_sys_timer_ii is
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generic(
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generic(
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Rd_Data : out DATA_TYPE;
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Rd_Data : out DATA_TYPE;
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Interrupt : out std_logic
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Interrupt : out std_logic
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);
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);
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end entity;
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end entity;
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architecture behave of o8_sys_timer_ii is
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architecture behave of o8_sys_timer_ii is
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alias Clock is Open8_Bus.Clock;
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alias Clock is Open8_Bus.Clock;
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alias Reset is Open8_Bus.Reset;
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alias Reset is Open8_Bus.Reset;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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alias uSec_Tick is Open8_Bus.uSec_Tick;
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constant User_Addr : std_logic_vector(15 downto 2) :=
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constant User_Addr : std_logic_vector(15 downto 2) :=
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Address(15 downto 2);
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Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Comp_Addr is Open8_Bus.Address(15 downto 2);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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alias Reg_Addr is Open8_Bus.Address(1 downto 0);
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signal Addr_Match : std_logic := '0';
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signal Addr_Match : std_logic := '0';
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
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signal Wr_En : std_logic := '0';
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signal Wr_En : std_logic := '0';
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Wr_Data_q : DATA_TYPE := x"00";
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signal Rd_En : std_logic := '0';
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signal Rd_En : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Req_Interval : std_logic_vector(23 downto 0) := x"000000";
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signal Req_Interval : std_logic_vector(23 downto 0) := x"000000";
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alias Req_Interval_B0 is Req_Interval( 7 downto 0);
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alias Req_Interval_B0 is Req_Interval( 7 downto 0);
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alias Req_Interval_B1 is Req_Interval(15 downto 8);
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alias Req_Interval_B1 is Req_Interval(15 downto 8);
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alias Req_Interval_B2 is Req_Interval(23 downto 16);
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alias Req_Interval_B2 is Req_Interval(23 downto 16);
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signal Int_Interval : std_logic_vector(23 downto 0) := x"000000";
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signal Int_Interval : std_logic_vector(23 downto 0) := x"000000";
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signal Update_Interval : std_logic := '0';
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signal Update_Interval : std_logic := '0';
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signal Update_Pending : std_logic := '0';
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signal Update_Pending : std_logic := '0';
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signal Output_Enable : std_logic := '0';
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signal Output_Enable : std_logic := '0';
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signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000";
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signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000";
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel <= "00";
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Reg_Sel <= "00";
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Wr_En <= '0';
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Wr_En <= '0';
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Wr_Data_q <= x"00";
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Wr_Data_q <= x"00";
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Rd_En <= '0';
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Rd_En <= '0';
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Req_Interval <= x"000000";
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Req_Interval <= x"000000";
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Update_Interval <= '0';
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Update_Interval <= '0';
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Update_Pending <= '0';
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Update_Pending <= '0';
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Output_Enable <= '0';
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Output_Enable <= '0';
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elsif( rising_edge( Clock ) )then
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elsif( rising_edge( Clock ) )then
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Reg_Sel <= Reg_Addr;
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Reg_Sel <= Reg_Addr;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En <= Addr_Match and Open8_Bus.Wr_En;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Wr_Data_q <= Open8_Bus.Wr_Data;
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Update_Interval <= '0';
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Update_Interval <= '0';
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if( Wr_En = '1' )then
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if( Wr_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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Req_Interval_B0 <= Wr_Data_q;
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Req_Interval_B0 <= Wr_Data_q;
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Update_Pending <= '1';
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Update_Pending <= '1';
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when "01" =>
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when "01" =>
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Req_Interval_B1 <= Wr_Data_q;
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Req_Interval_B1 <= Wr_Data_q;
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Update_Pending <= '1';
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Update_Pending <= '1';
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when "10" =>
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when "10" =>
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Req_Interval_B2 <= Wr_Data_q;
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Req_Interval_B2 <= Wr_Data_q;
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Update_Pending <= '1';
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Update_Pending <= '1';
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when "11" =>
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when "11" =>
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Output_Enable <= Wr_Data_q(7);
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Output_Enable <= Wr_Data_q(7);
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Update_Interval <= Wr_Data_q(6);
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Update_Interval <= Wr_Data_q(6);
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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if( Update_Interval = '1' )then
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if( Update_Interval = '1' )then
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Update_Pending <= '0';
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Update_Pending <= '0';
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end if;
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end if;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_Data <= OPEN8_NULLBUS;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En <= Addr_Match and Open8_Bus.Rd_En;
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if( Rd_En = '1' )then
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if( Rd_En = '1' )then
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case( Reg_Sel )is
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case( Reg_Sel )is
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when "00" =>
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when "00" =>
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Rd_Data <= Req_Interval_B0;
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Rd_Data <= Req_Interval_B0;
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when "01" =>
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when "01" =>
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Rd_Data <= Req_Interval_B1;
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Rd_Data <= Req_Interval_B1;
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when "10" =>
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when "10" =>
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Rd_Data <= Req_Interval_B2;
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Rd_Data <= Req_Interval_B2;
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when "11" =>
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when "11" =>
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Rd_Data <= Output_Enable & Update_Pending & "000000";
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Rd_Data <= Output_Enable & Update_Pending & "000000";
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when others => null;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Interval_proc: process( Clock, Reset )
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Interval_proc: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Int_Interval <= x"000000";
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Int_Interval <= x"000000";
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Timer_Cnt <= x"000000";
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Timer_Cnt <= x"000000";
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Interrupt <= '0';
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Interrupt <= '0';
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Timer_Cnt <= Timer_Cnt - uSec_Tick;
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Timer_Cnt <= Timer_Cnt - uSec_Tick;
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if( Update_Interval = '1' )then
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if( Update_Interval = '1' )then
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Int_Interval <= Req_Interval;
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Int_Interval <= Req_Interval;
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Timer_Cnt <= Req_Interval;
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Timer_Cnt <= Req_Interval;
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elsif( or_reduce(Timer_Cnt) = '0' )then
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elsif( or_reduce(Timer_Cnt) = '0' )then
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Timer_Cnt <= Int_Interval;
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Timer_Cnt <= Int_Interval;
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Interrupt <= Output_Enable;
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Interrupt <= Output_Enable;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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