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Line 20... |
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- VHDL Units : o8_sys_timer
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-- VHDL Units : o8_sys_timer
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-- Description: Provides an 8-bit microsecond resolution timer for generating
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-- Description: Provides an 24-bit microsecond resolution timer for generating
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-- : periodic interrupts for the Open8 CPU.
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-- : periodic interrupts for the Open8 CPU.
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--
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--
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-- Register Map:
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-- Register Map:
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-- Offset Bitfield Description Read/Write
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-- Offset Bitfield Description Read/Write
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-- 0x00 AAAAAAAA Req Interval Byte 0 (RW)
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-- 0x00 AAAAAAAA Req Interval Byte 0 (RW)
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| Line 45... |
Line 45... |
-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
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-- interval write.
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-- interval write.
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/16/20 Modified to use Open8 bus record
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-- Seth Henry 04/17/20 Altered interval to be a 24-bit counter
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-- Seth Henry 04/17/20 Altered interval to be a 24-bit counter
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 05/18/20 Added write qualification input
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-- Seth Henry 01/18/23 Added microsecond/millisecond generic
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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Line 59... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_sys_timer_ii is
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entity o8_sys_timer_ii is
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generic(
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generic(
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mSec_Resolution : boolean := FALSE;
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Write_Qual : in std_logic := '1';
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Write_Qual : in std_logic := '1';
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| Line 99... |
Line 102... |
signal Update_Interval : std_logic := '0';
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signal Update_Interval : std_logic := '0';
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signal Update_Pending : std_logic := '0';
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signal Update_Pending : std_logic := '0';
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signal Output_Enable : std_logic := '0';
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signal Output_Enable : std_logic := '0';
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signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000";
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signal Timer_Cnt : std_logic_vector(23 downto 0) := x"000000";
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constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
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conv_std_logic_vector(1000,10);
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signal mSec_Timer : std_logic_vector(9 downto 0) := (others => '0');
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signal Timer_Tick : std_logic := '0';
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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mSec_Resolution_enabled : if( mSec_Resolution )generate
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mSec_Tick_proc: process( Clock, Reset )
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begin
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if( Reset = Reset_Level )then
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mSec_Timer <= (others => '0');
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Timer_Tick <= '0';
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elsif( rising_edge(Clock) )then
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mSec_Timer <= mSec_Timer - uSec_Tick;
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Timer_Tick <= '0';
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if( mSec_Timer = 0 )then
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mSec_Timer <= MSEC_DELAY;
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Timer_Tick <= '1';
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end if;
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end if;
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end process;
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end generate;
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uSec_Resolution_enabled : if( not mSec_Resolution )generate
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Timer_Tick <= uSec_Tick;
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end generate;
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io_reg: process( Clock, Reset )
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io_reg: process( Clock, Reset )
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begin
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begin
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if( Reset = Reset_Level )then
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if( Reset = Reset_Level )then
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Reg_Sel_q <= "00";
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Reg_Sel_q <= "00";
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Wr_En_q <= '0';
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Wr_En_q <= '0';
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| Line 171... |
Line 206... |
Int_Interval <= x"000000";
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Int_Interval <= x"000000";
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Timer_Cnt <= x"000000";
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Timer_Cnt <= x"000000";
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Interrupt <= '0';
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Interrupt <= '0';
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elsif( rising_edge(Clock) )then
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elsif( rising_edge(Clock) )then
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Interrupt <= '0';
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Interrupt <= '0';
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Timer_Cnt <= Timer_Cnt - uSec_Tick;
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Timer_Cnt <= Timer_Cnt - Timer_Tick;
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if( Update_Interval = '1' )then
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if( Update_Interval = '1' )then
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Int_Interval <= Req_Interval;
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Int_Interval <= Req_Interval;
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Timer_Cnt <= Req_Interval;
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Timer_Cnt <= Req_Interval;
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elsif( or_reduce(Timer_Cnt) = '0' )then
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elsif( or_reduce(Timer_Cnt) = '0' )then
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Timer_Cnt <= Int_Interval;
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Timer_Cnt <= Int_Interval;
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