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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
[/] [open8_urisc/] [trunk/] [VHDL/] [o8_vdsm8.vhd] - Diff between revs 244 and 268
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| Rev 244 |
Rev 268 |
| Line 45... |
Line 45... |
library work;
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library work;
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use work.open8_pkg.all;
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use work.open8_pkg.all;
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entity o8_vdsm8 is
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entity o8_vdsm8 is
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generic(
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generic(
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Invert_Output : boolean := FALSE;
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Default_Value : DATA_TYPE := x"00";
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Default_Value : DATA_TYPE := x"00";
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Address : ADDRESS_TYPE
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Address : ADDRESS_TYPE
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);
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);
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port(
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port(
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Open8_Bus : in OPEN8_BUS_TYPE;
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Open8_Bus : in OPEN8_BUS_TYPE;
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Line 76... |
signal Rd_En_d : std_logic := '0';
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signal Rd_En_d : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Rd_En_q : std_logic := '0';
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signal Reg_Out : DATA_TYPE;
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signal Reg_Out : DATA_TYPE;
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signal DACout_pre : std_logic;
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begin
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begin
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
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| Line 112... |
Line 115... |
)
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)
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port map(
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port map(
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Clock => Clock,
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Clock => Clock,
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Reset => Reset,
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Reset => Reset,
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DACin => Reg_Out,
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DACin => Reg_Out,
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DACout => DACout
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DACout => DACout_pre
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);
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);
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DACout <= (not DACout_pre) when Invert_Output else
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DACout_pre;
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end architecture;
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end architecture;
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