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-- equations were taken from Intel/Altera app note AN049.
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-- equations were taken from Intel/Altera app note AN049.
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--
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--
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-- Revision History
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-- Revision History
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-- Author Date Change
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-- Author Date Change
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------------------ -------- ---------------------------------------------------
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------------------ -------- ---------------------------------------------------
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-- Seth Henry 04/14/20 Code cleanup and revision section added
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-- Seth Henry 12/09/20 Created from original version
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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use work.sdlc_serial_pkg.all;
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entity sdlc_crc16_ccitt is
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entity sdlc_crc16_ccitt is
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generic(
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generic(
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Poly_Init : std_logic_vector(15 downto 0) := x"0000";
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Reset_Level : std_logic := '1'
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Reset_Level : std_logic := '1'
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);
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);
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Clock : in std_logic;
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Clock : in std_logic;
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Reset : in std_logic;
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Reset : in std_logic;
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--
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--
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Clear : in std_logic;
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Clear : in std_logic;
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Wr_En : in std_logic;
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Wr_En : in std_logic;
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Wr_Data : in DATA_IN_TYPE;
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Wr_Data : in std_logic_vector(7 downto 0);
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--
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--
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CRC16_Valid : out std_logic;
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CRC16_Valid : out std_logic;
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CRC16_Out : out CRC_OUT_TYPE
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CRC16_Out : out std_logic_vector(15 downto 0)
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);
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);
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end entity;
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end entity;
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architecture behave of sdlc_crc16_ccitt is
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architecture behave of sdlc_crc16_ccitt is
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signal Calc_En : std_logic := '0';
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signal Calc_En : std_logic := '0';
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signal Buffer_En : std_logic := '0';
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signal Buffer_En : std_logic := '0';
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signal Data : DATA_IN_TYPE := x"00";
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signal Data : std_logic_vector(7 downto 0) := x"00";
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signal Exr : DATA_IN_TYPE := x"00";
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signal Exr : std_logic_vector(7 downto 0) := x"00";
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signal Reg : CRC_OUT_TYPE := x"0000";
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signal Reg : std_logic_vector(15 downto 0) := x"0000";
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begin
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begin
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Exr(0) <= Reg(0) xor Data(0);
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Exr(0) <= Reg(0) xor Data(0);
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Exr(1) <= Reg(1) xor Data(1);
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Exr(1) <= Reg(1) xor Data(1);
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