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[/] [open8_urisc/] [trunk/] [VHDL/] [sdlc_crc16_ccitt.vhd] - Diff between revs 265 and 278

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Rev 265 Rev 278
Line 26... Line 26...
--  equations were taken from Intel/Altera app note AN049.
--  equations were taken from Intel/Altera app note AN049.
--
--
-- Revision History
-- Revision History
-- Author          Date     Change
-- Author          Date     Change
------------------ -------- ---------------------------------------------------
------------------ -------- ---------------------------------------------------
-- Seth Henry      04/14/20 Code cleanup and revision section added
-- Seth Henry      12/09/20 Created from original version
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
 
 
library work;
 
  use work.sdlc_serial_pkg.all;
 
 
 
entity sdlc_crc16_ccitt is
entity sdlc_crc16_ccitt is
generic(
generic(
  Poly_Init                  : std_logic_vector(15 downto 0) := x"0000";
  Poly_Init                  : std_logic_vector(15 downto 0) := x"0000";
  Reset_Level                : std_logic := '1'
  Reset_Level                : std_logic := '1'
);
);
Line 45... Line 42...
  Clock                      : in  std_logic;
  Clock                      : in  std_logic;
  Reset                      : in  std_logic;
  Reset                      : in  std_logic;
  --
  --
  Clear                      : in  std_logic;
  Clear                      : in  std_logic;
  Wr_En                      : in  std_logic;
  Wr_En                      : in  std_logic;
  Wr_Data                    : in  DATA_IN_TYPE;
  Wr_Data                    : in  std_logic_vector(7 downto 0);
  --
  --
  CRC16_Valid                : out std_logic;
  CRC16_Valid                : out std_logic;
  CRC16_Out                  : out CRC_OUT_TYPE
  CRC16_Out                  : out std_logic_vector(15 downto 0)
);
);
end entity;
end entity;
 
 
architecture behave of sdlc_crc16_ccitt is
architecture behave of sdlc_crc16_ccitt is
 
 
  signal Calc_En             : std_logic    := '0';
  signal Calc_En             : std_logic    := '0';
  signal Buffer_En           : std_logic    := '0';
  signal Buffer_En           : std_logic    := '0';
  signal Data                : DATA_IN_TYPE := x"00";
  signal Data                : std_logic_vector(7 downto 0)  := x"00";
  signal Exr                 : DATA_IN_TYPE := x"00";
  signal Exr                 : std_logic_vector(7 downto 0)  := x"00";
  signal Reg                 : CRC_OUT_TYPE := x"0000";
  signal Reg                 : std_logic_vector(15 downto 0) := x"0000";
 
 
begin
begin
 
 
  Exr(0)                     <= Reg(0) xor Data(0);
  Exr(0)                     <= Reg(0) xor Data(0);
  Exr(1)                     <= Reg(1) xor Data(1);
  Exr(1)                     <= Reg(1) xor Data(1);

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