URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [vdsm8.vhd] - Diff between revs 220 and 310

Rev 220	Rev 310
Line 44...	Line 44...
`);`	`);`
`port(`	`port(`
`Clock : in std_logic;`	`Clock : in std_logic;`
`Reset : in std_logic;`	`Reset : in std_logic;`
`DACin : in std_logic_vector(DAC_Width-1 downto 0);`	`DACin : in std_logic_vector(DAC_Width-1 downto 0);`
	`DACadv : in std_logic := '1';`
`DACout : out std_logic`	`DACout : out std_logic`
`);`	`);`
`end entity;`	`end entity;`

`architecture behave of vdsm8 is`	`architecture behave of vdsm8 is`
Line 175...	Line 176...
`Divisor(DAC_Width-1 downto 0) <= DACin_q;`	`Divisor(DAC_Width-1 downto 0) <= DACin_q;`
`q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;`	`q <= conv_std_logic_vector(0,DIV_WIDTH) & Dividend;`
`count <= (others => '0');`	`count <= (others => '0');`
`end if;`	`end if;`

`Period_Ctr <= Period_Ctr - 1;`	`Period_Ctr <= Period_Ctr - DACadv;`
`Width_Ctr <= Width_Ctr - 1;`	`Width_Ctr <= Width_Ctr - DACadv;`

`DACout <= '1';`	`DACout <= '1';`
`if( Width_Ctr = 0 )then`	`if( Width_Ctr = 0 )then`
`DACout <= '0';`	`DACout <= '0';`
`Width_Ctr <= (others => '0');`	`Width_Ctr <= (others => '0');`
Line 193...	Line 194...

`end if;`	`end if;`
`end process;`	`end process;`

`end architecture;`	`end architecture;`

`No newline at end of file`	`No newline at end of file`