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[/] [open8_urisc/] [trunk/] [VHDL/] [vector_tx.vhd] - Diff between revs 240 and 268

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Rev 240	Rev 268
Line 63...	Line 63...
`signal mSec_Tick : std_logic;`	`signal mSec_Tick : std_logic;`

`signal Button_Pressed : std_logic := '0';`	`signal Button_Pressed : std_logic := '0';`
`signal Button_CoS : std_logic := '0';`	`signal Button_CoS : std_logic := '0';`

`type VEC_ARG_TYPE is array(0 to 15) of std_logic_vector(15 downto 0);`	`type VEC_ARG_TYPE is array(0 to 31) of std_logic_vector(15 downto 0);`
`constant VEC_ARGS : VEC_ARG_TYPE := (`	`constant VEC_ARGS : VEC_ARG_TYPE := (`
`x"0000",`	`x"0000",`
`x"1111",`	`x"0001",`
`x"2222",`	`x"0002",`
`x"3333",`	`x"0003",`
`x"4444",`	`x"0004",`
`x"5555",`	`x"0005",`
`x"6666",`	`x"0006",`
`x"7777",`	`x"0007",`
`x"8888",`	`x"0008",`
`x"9999",`	`x"0009",`
`x"AAAA",`	`x"000A",`
`x"BBBB",`	`x"000B",`
`x"CCCC",`	`x"000C",`
`x"DDDD",`	`x"000D",`
`x"EEEE",`	`x"000E",`
	`x"000F",`

	`x"0800",`
	`x"0866",`
	`x"0975",`
	`x"00AE",`
	`x"DEAD",`
	`x"BEEF",`
	`x"CAFE",`
	`x"BABE",`
	`x"DECA",`
	`x"A5A5",`
	`x"C3C3",`
	`x"0123",`
	`x"4567",`
	`x"89AB",`
	`x"CDEF",`
`x"FFFF"`	`x"FFFF"`
`);`	`);`

`alias Vector_Arg_Sel is Switches(9 downto 6);`	`alias Vector_Arg_Sel is Switches(9 downto 5);`
`alias Vector_Cmd_Sel is Switches(5 downto 0);`	`alias Vector_Cmd_Sel is Switches(4 downto 0);`

`signal Vector_Cmd : std_logic_vector(7 downto 0);`	`signal Vector_Cmd : std_logic_vector(7 downto 0);`

`signal Vector_Arg : std_logic_vector(15 downto 0);`	`signal Vector_Arg : std_logic_vector(15 downto 0);`
`alias Vector_Arg_LB is Vector_Arg(7 downto 0);`	`alias Vector_Arg_LB is Vector_Arg(7 downto 0);`
Line 137...	Line 154...
`begin`	`begin`
`if( Reset = Reset_Level )then`	`if( Reset = Reset_Level )then`
`Vector_Cmd <= x"00";`	`Vector_Cmd <= x"00";`
`Vector_Arg <= x"0000";`	`Vector_Arg <= x"0000";`
`elsif( rising_edge(Clock) )then`	`elsif( rising_edge(Clock) )then`
`Vector_Cmd <= "00" & Vector_Cmd_Sel;`	`Vector_Cmd <= "000" & Vector_Cmd_Sel;`
`Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));`	`Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));`
`end if;`	`end if;`
`end process;`	`end process;`

`TX_FSM_proc: process( Clock, Reset )`	`TX_FSM_proc: process( Clock, Reset )`

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[/] [open8_urisc/] [trunk/] [VHDL/] [vector_tx.vhd] - Diff between revs 240 and 268