| Line 722... |
Line 722... |
#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
|
#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
|
#define BAD_PC_ADDRESSING \
|
#define BAD_PC_ADDRESSING \
|
_("cannot use register index with PC-relative addressing")
|
_("cannot use register index with PC-relative addressing")
|
#define BAD_PC_WRITEBACK \
|
#define BAD_PC_WRITEBACK \
|
_("cannot use writeback with PC-relative addressing")
|
_("cannot use writeback with PC-relative addressing")
|
|
#define BAD_RANGE _("branch out of range")
|
|
|
static struct hash_control * arm_ops_hsh;
|
static struct hash_control * arm_ops_hsh;
|
static struct hash_control * arm_cond_hsh;
|
static struct hash_control * arm_cond_hsh;
|
static struct hash_control * arm_shift_hsh;
|
static struct hash_control * arm_shift_hsh;
|
static struct hash_control * arm_psr_hsh;
|
static struct hash_control * arm_psr_hsh;
|
| Line 756... |
Line 757... |
unsigned int next_free_entry;
|
unsigned int next_free_entry;
|
unsigned int id;
|
unsigned int id;
|
symbolS * symbol;
|
symbolS * symbol;
|
segT section;
|
segT section;
|
subsegT sub_section;
|
subsegT sub_section;
|
|
#ifdef OBJ_ELF
|
|
struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
|
|
#endif
|
struct literal_pool * next;
|
struct literal_pool * next;
|
} literal_pool;
|
} literal_pool;
|
|
|
/* Pointer to a linked list of literal pools. */
|
/* Pointer to a linked list of literal pools. */
|
literal_pool * list_of_pools = NULL;
|
literal_pool * list_of_pools = NULL;
|
| Line 2587... |
Line 2591... |
|
|
if (mapstate == state)
|
if (mapstate == state)
|
/* The mapping symbol has already been emitted.
|
/* The mapping symbol has already been emitted.
|
There is nothing else to do. */
|
There is nothing else to do. */
|
return;
|
return;
|
else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
|
|
|
if (state == MAP_ARM || state == MAP_THUMB)
|
|
/* PR gas/12931
|
|
All ARM instructions require 4-byte alignment.
|
|
(Almost) all Thumb instructions require 2-byte alignment.
|
|
|
|
When emitting instructions into any section, mark the section
|
|
appropriately.
|
|
|
|
Some Thumb instructions are alignment-sensitive modulo 4 bytes,
|
|
but themselves require 2-byte alignment; this applies to some
|
|
PC- relative forms. However, these cases will invovle implicit
|
|
literal pool generation or an explicit .align >=2, both of
|
|
which will cause the section to me marked with sufficient
|
|
alignment. Thus, we don't handle those cases here. */
|
|
record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
|
|
|
|
if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
|
/* This case will be evaluated later in the next else. */
|
/* This case will be evaluated later in the next else. */
|
return;
|
return;
|
else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
|
else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
|
|| TRANSITION (MAP_UNDEFINED, MAP_THUMB))
|
|| TRANSITION (MAP_UNDEFINED, MAP_THUMB))
|
{
|
{
|
| Line 3054... |
Line 3075... |
inst.error = _("literal pool overflow");
|
inst.error = _("literal pool overflow");
|
return FAIL;
|
return FAIL;
|
}
|
}
|
|
|
pool->literals[entry] = inst.reloc.exp;
|
pool->literals[entry] = inst.reloc.exp;
|
|
#ifdef OBJ_ELF
|
|
/* PR ld/12974: Record the location of the first source line to reference
|
|
this entry in the literal pool. If it turns out during linking that the
|
|
symbol does not exist we will be able to give an accurate line number for
|
|
the (first use of the) missing reference. */
|
|
if (debug_type == DEBUG_DWARF2)
|
|
dwarf2_where (pool->locs + entry);
|
|
#endif
|
pool->next_free_entry += 1;
|
pool->next_free_entry += 1;
|
}
|
}
|
|
|
inst.reloc.exp.X_op = O_symbol;
|
inst.reloc.exp.X_op = O_symbol;
|
inst.reloc.exp.X_add_number = ((int) entry) * 4;
|
inst.reloc.exp.X_add_number = ((int) entry) * 4;
|
| Line 3151... |
Line 3180... |
#if defined OBJ_COFF || defined OBJ_ELF
|
#if defined OBJ_COFF || defined OBJ_ELF
|
ARM_SET_INTERWORK (pool->symbol, support_interwork);
|
ARM_SET_INTERWORK (pool->symbol, support_interwork);
|
#endif
|
#endif
|
|
|
for (entry = 0; entry < pool->next_free_entry; entry ++)
|
for (entry = 0; entry < pool->next_free_entry; entry ++)
|
|
{
|
|
#ifdef OBJ_ELF
|
|
if (debug_type == DEBUG_DWARF2)
|
|
dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
|
|
#endif
|
/* First output the expression in the instruction to the pool. */
|
/* First output the expression in the instruction to the pool. */
|
emit_expr (&(pool->literals[entry]), 4); /* .word */
|
emit_expr (&(pool->literals[entry]), 4); /* .word */
|
|
}
|
|
|
/* Mark the pool as empty. */
|
/* Mark the pool as empty. */
|
pool->next_free_entry = 0;
|
pool->next_free_entry = 0;
|
pool->symbol = NULL;
|
pool->symbol = NULL;
|
}
|
}
|
| Line 6116... |
Line 6151... |
|
|
/* Optional operands. */
|
/* Optional operands. */
|
OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
|
OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
|
OP_oI31b, /* 0 .. 31 */
|
OP_oI31b, /* 0 .. 31 */
|
OP_oI32b, /* 1 .. 32 */
|
OP_oI32b, /* 1 .. 32 */
|
|
OP_oI32z, /* 0 .. 32 */
|
OP_oIffffb, /* 0 .. 65535 */
|
OP_oIffffb, /* 0 .. 65535 */
|
OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
|
OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
|
|
|
OP_oRR, /* ARM register */
|
OP_oRR, /* ARM register */
|
OP_oRRnpc, /* ARM register, not the PC */
|
OP_oRRnpc, /* ARM register, not the PC */
|
| Line 6445... |
Line 6481... |
case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
|
case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
|
case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
|
case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
|
case OP_oI31b:
|
case OP_oI31b:
|
case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
|
case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
|
case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
|
case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
|
|
case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
|
case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
|
case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
|
|
|
/* Immediate variants */
|
/* Immediate variants */
|
case OP_oI255c:
|
case OP_oI255c:
|
po_char_or_fail ('{');
|
po_char_or_fail ('{');
|
| Line 8462... |
Line 8499... |
inst.instruction |= inst.operands[2].reg << 16;
|
inst.instruction |= inst.operands[2].reg << 16;
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
inst.reloc.type = BFD_RELOC_UNUSED;
|
}
|
}
|
|
|
static void
|
static void
|
|
do_t_strexbh (void)
|
|
{
|
|
constraint (!inst.operands[2].isreg || !inst.operands[2].preind
|
|
|| inst.operands[2].postind || inst.operands[2].writeback
|
|
|| inst.operands[2].immisreg || inst.operands[2].shifted
|
|
|| inst.operands[2].negative,
|
|
BAD_ADDR_MODE);
|
|
|
|
constraint (inst.operands[0].reg == inst.operands[1].reg
|
|
|| inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
|
|
|
|
do_rm_rd_rn ();
|
|
}
|
|
|
|
static void
|
do_strexd (void)
|
do_strexd (void)
|
{
|
{
|
constraint (inst.operands[1].reg % 2 != 0,
|
constraint (inst.operands[1].reg % 2 != 0,
|
_("even register required"));
|
_("even register required"));
|
constraint (inst.operands[2].present
|
constraint (inst.operands[2].present
|
| Line 8734... |
Line 8786... |
}
|
}
|
|
|
static void
|
static void
|
vfp_conv (int srcsize)
|
vfp_conv (int srcsize)
|
{
|
{
|
unsigned immbits = srcsize - inst.operands[1].imm;
|
int immbits = srcsize - inst.operands[1].imm;
|
|
|
|
if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
|
|
{
|
|
/* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
|
|
i.e. immbits must be in range 0 - 16. */
|
|
inst.error = _("immediate value out of range, expected range [0, 16]");
|
|
return;
|
|
}
|
|
else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
|
|
{
|
|
/* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
|
|
i.e. immbits must be in range 0 - 31. */
|
|
inst.error = _("immediate value out of range, expected range [1, 32]");
|
|
return;
|
|
}
|
|
|
inst.instruction |= (immbits & 1) << 5;
|
inst.instruction |= (immbits & 1) << 5;
|
inst.instruction |= (immbits >> 1);
|
inst.instruction |= (immbits >> 1);
|
}
|
}
|
|
|
static void
|
static void
|
| Line 9436... |
Line 9504... |
inst.instruction |= Rs << 16;
|
inst.instruction |= Rs << 16;
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
|
unsigned int value = inst.reloc.exp.X_add_number;
|
|
unsigned int shift = inst.operands[2].shift_kind;
|
|
|
Rn = inst.operands[2].reg;
|
Rn = inst.operands[2].reg;
|
/* See if we can do this with a 16-bit instruction. */
|
/* See if we can do this with a 16-bit instruction. */
|
if (!inst.operands[2].shifted && inst.size_req != 4)
|
if (!inst.operands[2].shifted && inst.size_req != 4)
|
{
|
{
|
if (Rd > 7 || Rs > 7 || Rn > 7)
|
if (Rd > 7 || Rs > 7 || Rn > 7)
|
| Line 9486... |
Line 9557... |
constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
|
constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
|
_("shift must be constant"));
|
_("shift must be constant"));
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
inst.instruction = THUMB_OP32 (inst.instruction);
|
inst.instruction |= Rd << 8;
|
inst.instruction |= Rd << 8;
|
inst.instruction |= Rs << 16;
|
inst.instruction |= Rs << 16;
|
|
constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
|
|
_("shift value over 3 not allowed in thumb mode"));
|
|
constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
|
|
_("only LSL shift allowed in thumb mode"));
|
encode_thumb32_shifted_operand (2);
|
encode_thumb32_shifted_operand (2);
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
| Line 17454... |
Line 17529... |
TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
|
TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
|
rd_rn, rd_rn),
|
rd_rn, rd_rn),
|
TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
|
TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
|
rd_rn, rd_rn),
|
rd_rn, rd_rn),
|
TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
strex, rm_rd_rn),
|
strex, t_strexbh),
|
TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
|
strex, rm_rd_rn),
|
strex, t_strexbh),
|
TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
|
TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
|
|
|
#undef ARM_VARIANT
|
#undef ARM_VARIANT
|
#define ARM_VARIANT & arm_ext_sec
|
#define ARM_VARIANT & arm_ext_sec
|
#undef THUMB_VARIANT
|
#undef THUMB_VARIANT
|
| Line 18175... |
Line 18250... |
NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
|
NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
|
NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
|
NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
|
NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
|
|
|
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
|
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
|
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
|
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
|
nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
|
nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
|
nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
|
nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
|
|
|
|
|
| Line 20907... |
Line 20982... |
if (value & temp)
|
if (value & temp)
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
_("misaligned branch destination"));
|
_("misaligned branch destination"));
|
if ((value & (offsetT)0xfe000000) != (offsetT)0
|
if ((value & (offsetT)0xfe000000) != (offsetT)0
|
&& (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
|
&& (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
|
_("branch out of range"));
|
|
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
if (fixP->fx_done || !seg->use_rela_p)
|
{
|
{
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
newval = md_chars_to_number (buf, INSN_SIZE);
|
newval |= (value >> 2) & 0x00ffffff;
|
newval |= (value >> 2) & 0x00ffffff;
|
| Line 20944... |
Line 21018... |
md_number_to_chars (buf, newval, THUMB_SIZE);
|
md_number_to_chars (buf, newval, THUMB_SIZE);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (value & ~0x7e)
|
if (value & ~0x7e)
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
|
_("branch out of range"));
|
|
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
if (fixP->fx_done || !seg->use_rela_p)
|
{
|
{
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
|
newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
|
| Line 20958... |
Line 21031... |
}
|
}
|
break;
|
break;
|
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
|
case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
|
if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
|
if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
|
_("branch out of range"));
|
|
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
if (fixP->fx_done || !seg->use_rela_p)
|
{
|
{
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
newval |= (value & 0x1ff) >> 1;
|
newval |= (value & 0x1ff) >> 1;
|
| Line 20971... |
Line 21043... |
}
|
}
|
break;
|
break;
|
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
|
case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
|
if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
|
if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
|
_("branch out of range"));
|
|
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
if (fixP->fx_done || !seg->use_rela_p)
|
{
|
{
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
newval = md_chars_to_number (buf, THUMB_SIZE);
|
newval |= (value & 0xfff) >> 1;
|
newval |= (value & 0xfff) >> 1;
|
| Line 20992... |
Line 21063... |
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
&& ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
|
{
|
{
|
/* Force a relocation for a branch 20 bits wide. */
|
/* Force a relocation for a branch 20 bits wide. */
|
fixP->fx_done = 0;
|
fixP->fx_done = 0;
|
}
|
}
|
if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
|
if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
_("conditional branch out of range"));
|
_("conditional branch out of range"));
|
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
if (fixP->fx_done || !seg->use_rela_p)
|
{
|
{
|
| Line 21017... |
Line 21088... |
md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
|
md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
|
}
|
}
|
break;
|
break;
|
|
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
case BFD_RELOC_THUMB_PCREL_BLX:
|
|
|
/* If there is a blx from a thumb state function to
|
/* If there is a blx from a thumb state function to
|
another thumb function flip this to a bl and warn
|
another thumb function flip this to a bl and warn
|
about it. */
|
about it. */
|
|
|
if (fixP->fx_addsy
|
if (fixP->fx_addsy
|
| Line 21042... |
Line 21112... |
|
|
|
|
goto thumb_bl_common;
|
goto thumb_bl_common;
|
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
case BFD_RELOC_THUMB_PCREL_BRANCH23:
|
|
|
/* A bl from Thumb state ISA to an internal ARM state function
|
/* A bl from Thumb state ISA to an internal ARM state function
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is converted to a blx. */
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is converted to a blx. */
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if (fixP->fx_addsy
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if (fixP->fx_addsy
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&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
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&& (S_GET_SEGMENT (fixP->fx_addsy) == seg)
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&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
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&& !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
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| Line 21073... |
Line 21142... |
to a word boundary. This follows the semantics of the instruction
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to a word boundary. This follows the semantics of the instruction
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which specifies that bit 1 of the target address will come from bit
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which specifies that bit 1 of the target address will come from bit
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1 of the base address. */
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1 of the base address. */
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value = (value + 1) & ~ 1;
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value = (value + 1) & ~ 1;
|
|
|
|
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if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
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if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
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{
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{
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if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
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if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
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{
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as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
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as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
_("branch out of range"));
|
|
}
|
|
else if ((value & ~0x1ffffff)
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else if ((value & ~0x1ffffff)
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&& ((value & ~0x1ffffff) != ~0x1ffffff))
|
&& ((value & ~0x1ffffff) != ~0x1ffffff))
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{
|
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as_bad_where (fixP->fx_file, fixP->fx_line,
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as_bad_where (fixP->fx_file, fixP->fx_line,
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_("Thumb2 branch out of range"));
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_("Thumb2 branch out of range"));
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}
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}
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}
|
|
|
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if (fixP->fx_done || !seg->use_rela_p)
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if (fixP->fx_done || !seg->use_rela_p)
|
encode_thumb2_b_bl_offset (buf, value);
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encode_thumb2_b_bl_offset (buf, value);
|
|
|
break;
|
break;
|
|
|
case BFD_RELOC_THUMB_PCREL_BRANCH25:
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case BFD_RELOC_THUMB_PCREL_BRANCH25:
|
if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
|
if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
|
_("branch out of range"));
|
|
|
|
if (fixP->fx_done || !seg->use_rela_p)
|
if (fixP->fx_done || !seg->use_rela_p)
|
encode_thumb2_b_bl_offset (buf, value);
|
encode_thumb2_b_bl_offset (buf, value);
|
|
|
break;
|
break;
|
