| Line 35... |
Line 35... |
#define UBD INSN_UNCOND_BRANCH_DELAY
|
#define UBD INSN_UNCOND_BRANCH_DELAY
|
#define CBD INSN_COND_BRANCH_DELAY
|
#define CBD INSN_COND_BRANCH_DELAY
|
#define COD INSN_COPROC_MOVE_DELAY
|
#define COD INSN_COPROC_MOVE_DELAY
|
#define CLD INSN_COPROC_MEMORY_DELAY
|
#define CLD INSN_COPROC_MEMORY_DELAY
|
#define CBL INSN_COND_BRANCH_LIKELY
|
#define CBL INSN_COND_BRANCH_LIKELY
|
#define TRAP INSN_TRAP
|
#define NODS INSN_NO_DELAY_SLOT
|
|
#define TRAP INSN_NO_DELAY_SLOT
|
#define SM INSN_STORE_MEMORY
|
#define SM INSN_STORE_MEMORY
|
|
|
#define WR_d INSN_WRITE_GPR_D
|
#define WR_d INSN_WRITE_GPR_D
|
#define WR_t INSN_WRITE_GPR_T
|
#define WR_t INSN_WRITE_GPR_T
|
#define WR_31 INSN_WRITE_GPR_31
|
#define WR_31 INSN_WRITE_GPR_31
|
| Line 148... |
Line 149... |
(ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
|
(ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
|
certain fields of the DSP control register. For simplicity, we decide not
|
certain fields of the DSP control register. For simplicity, we decide not
|
to track dependencies of these fields.
|
to track dependencies of these fields.
|
However, "bposge32" is a branch instruction that depends on the "pos"
|
However, "bposge32" is a branch instruction that depends on the "pos"
|
field. In order to make sure that GAS does not reorder DSP instructions
|
field. In order to make sure that GAS does not reorder DSP instructions
|
that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
|
that writes the "pos" field and "bposge32", we add DSP_VOLA
|
attribute to those instructions that write the "pos" field. */
|
(INSN_NO_DELAY_SLOT) attribute to those instructions that write the "pos"
|
|
field. */
|
|
|
#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
|
#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
|
#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
|
#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
|
#define MOD_a WR_a|RD_a
|
#define MOD_a WR_a|RD_a
|
#define DSP_VOLA INSN_TRAP
|
#define DSP_VOLA INSN_NO_DELAY_SLOT
|
#define D32 INSN_DSP
|
#define D32 INSN_DSP
|
#define D33 INSN_DSPR2
|
#define D33 INSN_DSPR2
|
#define D64 INSN_DSP64
|
#define D64 INSN_DSP64
|
|
|
/* MIPS MT ASE support. */
|
/* MIPS MT ASE support. */
|
| Line 169... |
Line 171... |
#define WR_Z INSN2_WRITE_FPR_Z
|
#define WR_Z INSN2_WRITE_FPR_Z
|
#define RD_z INSN2_READ_GPR_Z
|
#define RD_z INSN2_READ_GPR_Z
|
#define RD_Z INSN2_READ_FPR_Z
|
#define RD_Z INSN2_READ_FPR_Z
|
#define RD_d INSN2_READ_GPR_D
|
#define RD_d INSN2_READ_GPR_D
|
|
|
|
/* MIPS MCU (MicroController) ASE support. */
|
|
#define MC INSN_MCU
|
|
|
/* The order of overloaded instructions matters. Label arguments and
|
/* The order of overloaded instructions matters. Label arguments and
|
register arguments look the same. Instructions that can have either
|
register arguments look the same. Instructions that can have either
|
for arguments must apear in the correct order in this table for the
|
for arguments must apear in the correct order in this table for the
|
assembler to pick the right one. In other words, entries with
|
assembler to pick the right one. In other words, entries with
|
immediate operands must apear after the same instruction with
|
immediate operands must apear after the same instruction with
|
| Line 268... |
Line 273... |
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
|
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
|
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
|
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
|
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
|
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
|
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F },
|
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F },
|
{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E },
|
{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E },
|
|
{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, MC },
|
|
{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC },
|
|
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC },
|
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
|
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
|
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
|
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
|
{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
|
{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
|
{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
|
{"add", "D,S,T", 0x4b40000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2F|IL3A },
|
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
|
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
|
| Line 308... |
Line 316... |
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
|
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
|
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
|
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
|
|
{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, MC },
|
|
{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC },
|
|
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC },
|
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
|
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
|
/* b is at the top of the table. */
|
/* b is at the top of the table. */
|
/* bal is at the top of the table. */
|
/* bal is at the top of the table. */
|
{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT },
|
{"bbit032", "s,+x,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT },
|
{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit032 */
|
{"bbit0", "s,+X,p", 0xd8000000, 0xfc000000, RD_s|CBD, 0, IOCT }, /* bbit032 */
|
| Line 629... |
Line 640... |
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
|
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
|
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
|
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
|
/* dctr and dctw are used on the r5000. */
|
/* dctr and dctw are used on the r5000. */
|
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
|
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
|
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
|
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
|
{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
|
{"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2 },
|
{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
|
{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
|
{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
/* For ddiv, see the comments about div. */
|
/* For ddiv, see the comments about div. */
|
| Line 761... |
Line 772... |
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
|
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
|
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
|
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
|
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
|
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
|
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3_32 },
|
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
|
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
|
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
|
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
|
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
|
{"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
{"exts32", "t,r,+p,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
{"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */
|
{"exts", "t,r,+P,+S",0x7000003b, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* exts32 */
|
| Line 774... |
Line 785... |
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
|
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
|
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
|
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
|
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
|
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
|
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
|
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
|
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
|
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
|
|
{"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC },
|
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
|
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
|
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
|
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
|
the same hazard barrier effect. */
|
the same hazard barrier effect. */
|
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
|
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
|
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
|
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
|
| Line 1398... |
Line 1410... |
{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
|
{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
|
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
|
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
|
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
|
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
|
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
|
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
|
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 },
|
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4_33 },
|
{"synciobdma", "", 0x0000008f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
{"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT },
|
{"syncs", "", 0x0000018f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
{"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT },
|
{"syncw", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
{"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT },
|
{"syncws", "", 0x0000014f, 0xffffffff, INSN_SYNC, 0, IOCT },
|
{"syncws", "", 0x0000014f, 0xffffffff, NODS, 0, IOCT },
|
{"sync_acquire", "", 0x0000044f, 0xffffffff, INSN_SYNC, 0, I33 },
|
{"sync_acquire", "", 0x0000044f, 0xffffffff, NODS, 0, I33 },
|
{"sync_mb", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I33 },
|
{"sync_mb", "", 0x0000040f, 0xffffffff, NODS, 0, I33 },
|
{"sync_release", "", 0x0000048f, 0xffffffff, INSN_SYNC, 0, I33 },
|
{"sync_release", "", 0x0000048f, 0xffffffff, NODS, 0, I33 },
|
{"sync_rmb", "", 0x000004cf, 0xffffffff, INSN_SYNC, 0, I33 },
|
{"sync_rmb", "", 0x000004cf, 0xffffffff, NODS, 0, I33 },
|
{"sync_wmb", "", 0x0000010f, 0xffffffff, INSN_SYNC, 0, I33 },
|
{"sync_wmb", "", 0x0000010f, 0xffffffff, NODS, 0, I33 },
|
{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
|
{"sync", "", 0x0000000f, 0xffffffff, NODS, 0, I2|G1 },
|
{"sync", "1", 0x0000000f, 0xfffff83f, INSN_SYNC, 0, I32 },
|
{"sync", "1", 0x0000000f, 0xfffff83f, NODS, 0, I32 },
|
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
|
{"sync.p", "", 0x0000040f, 0xffffffff, NODS, 0, I2 },
|
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
|
{"sync.l", "", 0x0000000f, 0xffffffff, NODS, 0, I2 },
|
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
|
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
|
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
|
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
|
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
|
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
|
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
|
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
|
{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
|
{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
|
| Line 1479... |
Line 1491... |
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
|
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
|
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
|
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
|
{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
|
{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
|
{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
|
{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
|
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
|
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
|
{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3_32 },
|
{"wait", "", 0x42000020, 0xffffffff, NODS, 0, I3_32 },
|
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
|
{"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55 },
|
{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
|
{"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1 },
|
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
|
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
|
{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
|
{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
|
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
|
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
|
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
|
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
|
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
|
{"xor", "D,S,T", 0x47800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2E },
|
| Line 1494... |
Line 1506... |
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
|
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
|
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
|
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
|
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
|
{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
|
{"yield", "s", 0x7c000009, 0xfc1fffff, NODS|RD_s, 0, MT32 },
|
{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
|
{"yield", "d,s", 0x7c000009, 0xfc1f07ff, NODS|WR_d|RD_s, 0, MT32 },
|
|
|
/* User Defined Instruction. */
|
/* User Defined Instruction. */
|
{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
|
{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
|
{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
|
{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
|
{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
|
{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
|
