Line 65... |
Line 65... |
REL_DELAY2 = 3'd5,
|
REL_DELAY2 = 3'd5,
|
REL_WR2FL = 3'd6;
|
REL_WR2FL = 3'd6;
|
|
|
reg sm_rel_ctrl;
|
reg sm_rel_ctrl;
|
reg sm_rel_wren;
|
reg sm_rel_wren;
|
|
reg sm_rel_ctrl_mask;
|
|
reg sm_rel_ctrl_mask_clr;
|
|
reg sm_rel_ctrl_mask_set;
|
|
|
reg rden_r1;
|
|
reg int_rden;
|
reg int_rden;
|
reg int_rden_r1;
|
|
reg load_req_r1;
|
reg load_req_r1;
|
reg [RAM_ADDR_W-1:0] usr_ram_rd_addr_r1;
|
reg [RAM_ADDR_W-1:0] usr_ram_rd_addr_r1;
|
|
|
altsyncram3 ram (
|
altsyncram3 ram (
|
.data (din),
|
.data (din),
|
Line 222... |
Line 223... |
always @*
|
always @*
|
begin
|
begin
|
rel_req_from_idle = 1'b0;
|
rel_req_from_idle = 1'b0;
|
int_rden = 1'b0;
|
int_rden = 1'b0;
|
load_rel_ack = 1'b0;
|
load_rel_ack = 1'b0;
|
|
sm_rel_ctrl_mask_set = 1'b0;
|
|
sm_rel_ctrl_mask_clr = 1'b0;
|
sm_rel_ctrl = 1'b1;
|
sm_rel_ctrl = 1'b1;
|
sm_rel_wren = 1'b0;
|
sm_rel_wren = 1'b0;
|
case(cs_rd_sm)
|
case(cs_rd_sm)
|
IDLE:
|
IDLE:
|
begin
|
begin
|
rel_req_from_idle = rel_req;
|
rel_req_from_idle = rel_req;
|
sm_rel_ctrl = rel_req;
|
sm_rel_ctrl_mask_set = rel_req;
|
|
sm_rel_ctrl = 1'b0;
|
end
|
end
|
PREFETCH:
|
PREFETCH:
|
begin
|
begin
|
int_rden = 1'b1;
|
int_rden = 1'b1;
|
load_rel_ack = 1'b1;
|
load_rel_ack = 1'b1;
|
Line 246... |
Line 250... |
begin
|
begin
|
load_rel_ack = rel_req;
|
load_rel_ack = rel_req;
|
end
|
end
|
REL_DELAY1:
|
REL_DELAY1:
|
begin
|
begin
|
|
sm_rel_ctrl = ~sm_rel_ctrl_mask;
|
end
|
end
|
REL_DELAY2:
|
REL_DELAY2:
|
begin
|
begin
|
|
sm_rel_ctrl = ~sm_rel_ctrl_mask;
|
end
|
end
|
REL_WR2FL:
|
REL_WR2FL:
|
begin
|
begin
|
sm_rel_wren = 1'b1;
|
sm_rel_wren = 1'b1;
|
load_rel_ack = ll_q[0];
|
load_rel_ack = ll_q[0];
|
|
sm_rel_ctrl_mask_clr = 1'b1;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
always @ (posedge clk, negedge reset_n)
|
always @ (posedge clk, negedge reset_n)
|
begin
|
begin
|
if (reset_n==1'b0)
|
if (reset_n==1'b0)
|
begin
|
begin
|
cs_rd_sm <= 3'd0;
|
cs_rd_sm <= 3'd0;
|
rden_r1 <= 1'b0;
|
|
int_rden_r1 <= 1'b0;
|
|
load_req_r1 <= 1'b0;
|
load_req_r1 <= 1'b0;
|
|
sm_rel_ctrl_mask <= 1'b0;
|
ll_rd_addr <= {FL_ADDR_W{1'b0}};
|
ll_rd_addr <= {FL_ADDR_W{1'b0}};
|
ram_rd_addr <= {RAM_ADDR_W{1'b0}};
|
ram_rd_addr <= {RAM_ADDR_W{1'b0}};
|
usr_ram_rd_addr_r1 <= {RAM_ADDR_W{1'b0}};
|
usr_ram_rd_addr_r1 <= {RAM_ADDR_W{1'b0}};
|
fl_wren <= 1'b0;
|
fl_wren <= 1'b0;
|
fl_data <= {FL_W{1'b0}};
|
fl_data <= {FL_W{1'b0}};
|
end
|
end
|
else
|
else
|
begin
|
begin
|
cs_rd_sm <= ns_rd_sm;
|
cs_rd_sm <= ns_rd_sm;
|
rden_r1 <= rden;
|
|
int_rden_r1 <= int_rden;
|
|
load_req_r1 <= load_req;
|
load_req_r1 <= load_req;
|
|
sm_rel_ctrl_mask <= sm_rel_ctrl_mask_set ? 1'b1 :
|
|
sm_rel_ctrl_mask_clr ? 1'b0 :
|
|
sm_rel_ctrl_mask;
|
|
|
ll_rd_addr <= load_req_p || rel_req_from_idle ? chunk_num :
|
ll_rd_addr <= load_req_p || rel_req_from_idle ? chunk_num :
|
sm_rel_wren || ((!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)))) ? nxt_chunk_ptr :
|
sm_rel_wren || ((!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)))) ? nxt_chunk_ptr :
|
ll_rd_addr;
|
ll_rd_addr;
|
ram_rd_addr <= load_req_p ? {chunk_num, {IN_CNK_ADDR_W{1'b0}}} :
|
ram_rd_addr <= load_req_p ? {chunk_num, {IN_CNK_ADDR_W{1'b0}}} :
|