| Line 65... |
Line 65... |
REL_DELAY2 = 3'd5,
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REL_DELAY2 = 3'd5,
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REL_WR2FL = 3'd6;
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REL_WR2FL = 3'd6;
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reg sm_rel_ctrl;
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reg sm_rel_ctrl;
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reg sm_rel_wren;
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reg sm_rel_wren;
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reg sm_rel_ctrl_mask;
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reg sm_rel_ctrl_mask_clr;
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reg sm_rel_ctrl_mask_set;
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reg rden_r1;
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reg int_rden;
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reg int_rden;
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reg int_rden_r1;
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reg load_req_r1;
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reg load_req_r1;
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reg [RAM_ADDR_W-1:0] usr_ram_rd_addr_r1;
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reg [RAM_ADDR_W-1:0] usr_ram_rd_addr_r1;
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altsyncram3 ram (
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altsyncram3 ram (
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.data (din),
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.data (din),
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| Line 222... |
Line 223... |
always @*
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always @*
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begin
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begin
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rel_req_from_idle = 1'b0;
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rel_req_from_idle = 1'b0;
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int_rden = 1'b0;
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int_rden = 1'b0;
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load_rel_ack = 1'b0;
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load_rel_ack = 1'b0;
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sm_rel_ctrl_mask_set = 1'b0;
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sm_rel_ctrl_mask_clr = 1'b0;
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sm_rel_ctrl = 1'b1;
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sm_rel_ctrl = 1'b1;
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sm_rel_wren = 1'b0;
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sm_rel_wren = 1'b0;
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case(cs_rd_sm)
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case(cs_rd_sm)
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IDLE:
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IDLE:
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begin
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begin
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rel_req_from_idle = rel_req;
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rel_req_from_idle = rel_req;
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sm_rel_ctrl = rel_req;
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sm_rel_ctrl_mask_set = rel_req;
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sm_rel_ctrl = 1'b0;
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end
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end
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PREFETCH:
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PREFETCH:
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begin
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begin
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int_rden = 1'b1;
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int_rden = 1'b1;
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load_rel_ack = 1'b1;
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load_rel_ack = 1'b1;
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| Line 246... |
Line 250... |
begin
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begin
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load_rel_ack = rel_req;
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load_rel_ack = rel_req;
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end
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end
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REL_DELAY1:
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REL_DELAY1:
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begin
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begin
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sm_rel_ctrl = ~sm_rel_ctrl_mask;
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end
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end
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REL_DELAY2:
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REL_DELAY2:
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begin
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begin
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sm_rel_ctrl = ~sm_rel_ctrl_mask;
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end
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end
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REL_WR2FL:
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REL_WR2FL:
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begin
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begin
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sm_rel_wren = 1'b1;
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sm_rel_wren = 1'b1;
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load_rel_ack = ll_q[0];
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load_rel_ack = ll_q[0];
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sm_rel_ctrl_mask_clr = 1'b1;
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end
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end
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endcase
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endcase
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end
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end
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|
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always @ (posedge clk, negedge reset_n)
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always @ (posedge clk, negedge reset_n)
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begin
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begin
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if (reset_n==1'b0)
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if (reset_n==1'b0)
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begin
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begin
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cs_rd_sm <= 3'd0;
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cs_rd_sm <= 3'd0;
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rden_r1 <= 1'b0;
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int_rden_r1 <= 1'b0;
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load_req_r1 <= 1'b0;
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load_req_r1 <= 1'b0;
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sm_rel_ctrl_mask <= 1'b0;
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ll_rd_addr <= {FL_ADDR_W{1'b0}};
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ll_rd_addr <= {FL_ADDR_W{1'b0}};
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ram_rd_addr <= {RAM_ADDR_W{1'b0}};
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ram_rd_addr <= {RAM_ADDR_W{1'b0}};
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usr_ram_rd_addr_r1 <= {RAM_ADDR_W{1'b0}};
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usr_ram_rd_addr_r1 <= {RAM_ADDR_W{1'b0}};
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fl_wren <= 1'b0;
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fl_wren <= 1'b0;
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fl_data <= {FL_W{1'b0}};
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fl_data <= {FL_W{1'b0}};
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end
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end
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else
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else
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begin
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begin
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cs_rd_sm <= ns_rd_sm;
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cs_rd_sm <= ns_rd_sm;
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rden_r1 <= rden;
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int_rden_r1 <= int_rden;
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load_req_r1 <= load_req;
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load_req_r1 <= load_req;
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sm_rel_ctrl_mask <= sm_rel_ctrl_mask_set ? 1'b1 :
|
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sm_rel_ctrl_mask_clr ? 1'b0 :
|
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sm_rel_ctrl_mask;
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|
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ll_rd_addr <= load_req_p || rel_req_from_idle ? chunk_num :
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ll_rd_addr <= load_req_p || rel_req_from_idle ? chunk_num :
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sm_rel_wren || ((!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)))) ? nxt_chunk_ptr :
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sm_rel_wren || ((!sm_rel_ctrl && rden && (usr_ram_rd_addr_r1[IN_CNK_ADDR_W-1:0]==(LINES_IN_CNK-1)))) ? nxt_chunk_ptr :
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ll_rd_addr;
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ll_rd_addr;
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ram_rd_addr <= load_req_p ? {chunk_num, {IN_CNK_ADDR_W{1'b0}}} :
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ram_rd_addr <= load_req_p ? {chunk_num, {IN_CNK_ADDR_W{1'b0}}} :
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