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As a demonstration project, I'd love to implement an NTP server within the device. This is a long term goal, however, and a lot needs to be accomplished before I can get there. Still, a $130 NTP server isn't a bad price for an NTP server in your lab. ($99 for the Arty, $25 for the GPS receiver IIRC)
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As a demonstration project, I'd love to implement an NTP server within the device. This is a long term goal, however, and a lot needs to be accomplished before I can get there. Still, a $130 NTP server isn't a bad price for an NTP server in your lab. ($99 for the Arty, $25 for the GPS receiver IIRC)
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# Current Status
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# Current Status
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I currently have all the hardware on my desk.
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This version of the OpenArty project is designed to support an 8-bit byte branch of the ZipCPU. Once the ZipCPU is proven here and in some other locations, the 8-bit branch of the ZipCPU will become the master.
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The design builds, as of 20160910, at an 81.25 MHz clock speed.
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The design builds, as of 201710, at an 81.25 MHz clock speed, with the ZipCPU 8-bit byte updates. As of this writing, the design builds only. It has yet to be tested on the hardware (again--the trunk works on the hardware).
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- ZipCPU: The ZipCPU should be fully functional at the current clock speed. I'd like to boost it to twice this speed, but that may remain a longer term project.
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- ZipCPU: The ZipCPU should be fully functional at the current clock speed. I'd like to boost it to twice this speed, but that may remain a longer term project.
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- Flash: the flash controller has now passedd all of the tests given it, both simulated and live. It can read and write the flash, and so it can place configurations onto the flash as desired. As built, though, the controller is optimized for a 200MHz clock speed, and a 100MHz bus speed. It's being run at an 81.25MHz clock speed though (40.625MHz bus speed), so some performance improvement might yet be achieved.
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- Flash: Working completely. An option remains to increase the clock speed from one half of the system clock 81.25MHz, up to the actual system clock speed or perhaps even twice that speed.
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- SDRAM: I intend to implement work from the DDR3 SDRAM controller for the Arty. For now, the project builds with a Xilinx Memory Interface Generated (MIG) core, and a pipelind wishbone to AXI translator.
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- SDRAM: I would still like to implement the work from the DDR3 SDRAM controller for the Arty. For now, the project builds with a Xilinx Memory Interface Generated (MIG) core, and a pipelind wishbone to AXI translator.
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- NET: The entire network functionality has now been built, and preliminary testing suggests that it is fully functional.
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- NET: Working on the trunk using a simple program that can send and receive ARP packets, respond to ARP requests, respond to pings, and even ping a local host.
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- SD: The SDSPI controller has been integrated into the device, yet not tested yet. I don't expect issues with it, as it is a proven controller--just not one proven (yet) in this platform. Work remains to turn this from a SPI controller to an SDIO based driver.
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- SD: The SDSPI controller has been integrated into the device, yet not tested yet. I don't expect issues with it, as it is a proven controller--just not one proven (yet) in this platform. Work remains to turn this from a SPI controller to an SDIO based driver.
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- OLEDRGB: this driver is built, and has been integrated into the project, but testing hasn't started yet.
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- OLEDRGB: Working on the trunk
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So ... it's a work in progress.
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So ... it's a work in progress.
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# Repository
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# Repository
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