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Line 34... |
//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module bigsmpy(i_clk, i_sync, i_sgn, i_a, i_b, o_r, o_sync);
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module bigsmpy(i_clk, i_sync, i_sgn, i_a, i_b, o_r, o_sync);
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parameter CLOCKS = 1;
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input i_clk, i_sync, i_sgn;
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input i_clk, i_sync, i_sgn;
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input [31:0] i_a, i_b;
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input [31:0] i_a, i_b;
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output reg [63:0] o_r;
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output reg [63:0] o_r;
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output reg o_sync;
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output reg o_sync;
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generate
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if (CLOCKS == 1)
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begin
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wire signed [31:0] w_sa, w_sb;
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wire [31:0] w_ua, w_ub;
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assign w_sa = i_a;
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assign w_sb = i_b;
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assign w_ua = i_a;
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assign w_ub = i_b;
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always @(posedge i_clk)
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begin
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o_sync <= i_sync;
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if (i_sgn)
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o_r <= w_sa * w_sb;
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else
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o_r <= w_ua * w_ub;
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end
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end else if (CLOCKS == 2)
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begin
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reg signed [31:0] r_sa, r_sb;
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wire [31:0] w_ua, w_ub;
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always @(posedge i_clk)
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begin
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r_sa = i_a;
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r_sb = i_b;
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end
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assign w_ua = r_sa;
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assign w_ub = r_sb;
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always @(posedge i_clk)
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begin
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o_sync <= i_sync;
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if (i_sgn)
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o_r <= r_sa * r_sb;
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else
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o_r <= w_ua * w_ub;
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end
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end else if (CLOCKS == 5)
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begin
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//
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// A pipeline, shift register, to track our
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// synchronization pulse as it transits our pipeline
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//
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//
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// A pipeline, shift register, to track our synchronization pulse
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reg [3:0] r_s;
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reg [3:0] r_s;
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//
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//
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// Clock #1: Register our inputs, copy the value of the sign
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// bit.
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reg r_mpy_signed;
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reg r_mpy_signed;
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reg [31:0] r_mpy_a_input, r_mpy_b_input;
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reg [31:0] r_mpy_a_input, r_mpy_b_input;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (i_sgn)
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if (i_sgn)
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begin
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begin
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// This is about more than making the inputs
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// unsigned, as you'll notice it makes positive
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// inputs otherwise negative. Instead,
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// this is about making the inputs have offset
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// mode. Hence
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// i_a = r_mpy_a_input - 2^31
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// and so forth
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r_mpy_a_input <= {(~i_a[31]), i_a[30:0] };
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r_mpy_a_input <= {(~i_a[31]), i_a[30:0] };
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r_mpy_b_input <= {(~i_b[31]), i_b[30:0] };
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r_mpy_b_input <= {(~i_b[31]), i_b[30:0] };
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end else begin
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end else begin
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r_mpy_a_input <= i_a[31:0];
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r_mpy_a_input <= i_a[31:0];
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r_mpy_b_input <= i_b[31:0];
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r_mpy_b_input <= i_b[31:0];
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| Line 95... |
Line 153... |
reg [31:0] partial_mpy_2lo, partial_mpy_2hi;
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reg [31:0] partial_mpy_2lo, partial_mpy_2hi;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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partial_mpy_2lo[15:0] <= partial_mpy_lo[15:0];
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partial_mpy_2lo[15:0] <= partial_mpy_lo[15:0];
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{ partial_mpy_2cl, partial_mpy_2lo[31:16] }
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{ partial_mpy_2cl, partial_mpy_2lo[31:16] }
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<= { 1'b0, partial_mpy_oi[15:0]}+ partial_mpy_lo[32:16];
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<= { 1'b0, partial_mpy_oi[15:0]}
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+ partial_mpy_lo[32:16];
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{ partial_mpy_2ch, partial_mpy_2hi[16:0] }
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{ partial_mpy_2ch, partial_mpy_2hi[16:0] }
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<= partial_mpy_oi[32:16] + partial_mpy_hi[16:0];
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<= partial_mpy_oi[32:16] + partial_mpy_hi[16:0];
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partial_mpy_2hi[31:16] <= { partial_mpy_2hi[31:17], 1'b0 };
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partial_mpy_2hi[31:16] <= { partial_mpy_2hi[31:17],
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1'b0 };
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r_s[3] <= r_s[2];
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r_s[3] <= r_s[2];
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end
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end
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_r[31: 0] <= partial_mpy_2lo[31:0];
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o_r[31: 0] <= partial_mpy_2lo[31:0];
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o_r[63:32] <= partial_mpy_2hi
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o_r[63:32] <= partial_mpy_2hi
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+ { 13'h0, partial_mpy_2ch, 1'b0,
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+ { 14'h0, partial_mpy_2ch, 1'b0,
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15'h0, partial_mpy_2cl };
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15'h0, partial_mpy_2cl };
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o_sync <= r_s[3];
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o_sync <= r_s[3];
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end
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end
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end endgenerate
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endmodule
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endmodule
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