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//
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//
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// Filename: bigsmpy.v
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// Filename: bigsmpy.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose: To multiply two 32-bit numbers into a 64-bit number. We try
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// to use the hardware multiply to do this, but just what kind of
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// hardware multiply is actually available ... can be used to determine
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// how many clocks to take.
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//
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// If you look at the algorithm below, it's actually a series of a couple
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// of independent algorithms dependent upon the parameter NCLOCKS. If your
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// timing through here becomes a problem, set NCLOCKS to a higher number
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// and see if that doesn't help things.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module bigsmpy(i_clk, i_sync, i_sgn, i_a, i_b, o_r, o_sync);
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module bigsmpy(i_clk, i_sync, i_sgn, i_a, i_b, o_r, o_sync);
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parameter CLOCKS = 1;
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parameter NCLOCKS = 1;
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input i_clk, i_sync, i_sgn;
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input i_clk, i_sync, i_sgn;
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input [31:0] i_a, i_b;
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input [31:0] i_a, i_b;
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output reg [63:0] o_r;
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output reg [63:0] o_r;
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output reg o_sync;
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output reg o_sync;
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generate
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generate
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if (CLOCKS == 1)
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if (NCLOCKS == 1)
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begin
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begin
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wire signed [31:0] w_sa, w_sb;
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wire signed [31:0] w_sa, w_sb;
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wire [31:0] w_ua, w_ub;
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wire [31:0] w_ua, w_ub;
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assign w_sa = i_a;
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assign w_sa = i_a;
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o_r <= w_sa * w_sb;
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o_r <= w_sa * w_sb;
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else
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else
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o_r <= w_ua * w_ub;
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o_r <= w_ua * w_ub;
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end
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end
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end else if (CLOCKS == 2)
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end else if (NCLOCKS == 2)
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begin
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begin
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reg r_sync;
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reg signed [31:0] r_sa, r_sb;
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reg signed [31:0] r_sa, r_sb;
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wire [31:0] w_ua, w_ub;
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wire [31:0] w_ua, w_ub;
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initial r_sync = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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r_sa = i_a;
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r_sync <=i_sync;
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r_sb = i_b;
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r_sa <= i_a;
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r_sb <= i_b;
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end
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end
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assign w_ua = r_sa;
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assign w_ua = r_sa;
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assign w_ub = r_sb;
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assign w_ub = r_sb;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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o_sync <= i_sync;
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o_sync <= r_sync;
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if (i_sgn)
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if (i_sgn)
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o_r <= r_sa * r_sb;
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o_r <= r_sa * r_sb;
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else
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else
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o_r <= w_ua * w_ub;
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o_r <= w_ua * w_ub;
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end
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end
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end else if (CLOCKS == 5)
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end else if (NCLOCKS == 5)
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begin
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begin
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//
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//
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// A pipeline, shift register, to track our
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// A pipeline, shift register, to track our
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// synchronization pulse as it transits our pipeline
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// synchronization pulse as it transits our pipeline
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//
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//
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