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//
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//
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// Filename: bigsub.v
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// Filename: bigsub.v
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//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose: To subtract two 64-bit numbers, while maintaining
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// synchronization to whatever purpose these numbers had
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// originally. For this reason, there is an i_sync input and an o_sync
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// output. If i_sync is true with a particular set of data, o_sync will
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// then be true when that data is placed on the output.
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//
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// If we needed to slow this down even more, I suppose we could register
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// the inputs before we used them ...
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module bigsub(i_clk, i_sync, i_a, i_b, o_r, o_sync);
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module bigsub(i_clk, i_sync, i_a, i_b, o_r, o_sync);
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parameter NCLOCKS = 1;
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input i_clk, i_sync;
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input i_clk, i_sync;
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input [63:0] i_a, i_b;
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input [63:0] i_a, i_b;
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output reg [63:0] o_r;
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output wire [63:0] o_r;
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output reg o_sync;
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output wire o_sync;
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generate
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if (NCLOCKS == 0)
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begin
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assign o_sync= i_sync;
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assign o_r = i_a - i_b;
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end else if (NCLOCKS == 1)
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begin
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reg r_sync;
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reg [63:0] r_out;
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always @(posedge i_clk)
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r_sync <= i_sync;
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always @(posedge i_clk)
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r_out <= i_a - i_b;
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assign o_sync = r_sync;
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assign o_r = r_out;
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end else // if (NCLOCKS == 2)
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begin
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reg r_sync, r_pps;
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reg r_sync, r_pps;
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reg [31:0] r_hi_a, r_hi_b, r_low;
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reg [31:0] r_hi, r_low;
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reg [63:0] f_r;
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reg f_sync;
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wire [63:0] i_b_n;
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assign i_b_n = ~i_b;
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initial r_sync = 1'b0;
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initial r_sync = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_sync <= i_sync;
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r_sync <= i_sync;
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always @(posedge i_clk)
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always @(posedge i_clk)
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{ r_pps, r_low } <= i_a[31:0] + ({1'b1,~i_b[31:0]}) + 1'b1;
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{ r_pps, r_low } <= i_a[31:0] + i_b_n[31:0] + 1'b1;
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always @(posedge i_clk)
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r_hi_a <= i_a[63:32];
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_hi_b <= ~i_b[63:32];
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r_hi <= i_a[63:32] + i_b_n[63:32];
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initial o_sync = 1'b0;
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initial f_sync = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_sync <= r_sync;
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f_sync <= r_sync;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_r[31:0] <= r_low;
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f_r[31:0] <= r_low;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_r[63:32] <= r_hi_a + r_hi_b + { 31'h00, r_pps };
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f_r[63:32] <= r_hi + { 31'h00, r_pps };
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assign o_sync = f_sync;
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assign o_r = f_r;
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end endgenerate
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endmodule
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endmodule
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