| Line 12... |
Line 12... |
// Creator: Dan Gisselquist, Ph.D.
|
// Creator: Dan Gisselquist, Ph.D.
|
// Gisselquist Technology, LLC
|
// Gisselquist Technology, LLC
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
|
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
|
//
|
//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This program is free software (firmware): you can redistribute it and/or
|
// modify it under the terms of the GNU General Public License as published
|
// modify it under the terms of the GNU General Public License as published
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// your option) any later version.
|
// your option) any later version.
|
| Line 25... |
Line 25... |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// for more details.
|
// for more details.
|
//
|
//
|
// You should have received a copy of the GNU General Public License along
|
// You should have received a copy of the GNU General Public License along
|
// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
// target there if the PDF file isn't present.) If not, see
|
// target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
|
// <http://www.gnu.org/licenses/> for a copy.
|
//
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/gpl.html
|
| Line 111... |
Line 111... |
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
|
// Boad I/O
|
// Boad I/O
|
i_sw, i_btn, o_led,
|
i_sw, i_btn, o_led,
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
// PMod I/O
|
// PMod I/O
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n, i_gps_rx, o_gps_tx,
|
// The Quad SPI Flash
|
// The Quad SPI Flash
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
|
|
//
|
// The DDR3 SDRAM
|
// The DDR3 SDRAM
|
|
//
|
// The actual wires need to be controlled from the device
|
// The actual wires need to be controlled from the device
|
// dependent file. In order to keep this device independent,
|
// dependent file. In order to keep this device independent,
|
// we export only the wishbone interface to the RAM.
|
// we export only the wishbone interface to the RAM.
|
|
//
|
// o_ddr_ck_p, o_ddr_ck_n, o_ddr_reset_n, o_ddr_cke,
|
// o_ddr_ck_p, o_ddr_ck_n, o_ddr_reset_n, o_ddr_cke,
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,
|
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm,
|
// io_ddr_dqs_p, io_ddr_dqs_n, io_ddr_data,
|
// o_ddr_dqs, i_ddr_data, o_ddr_data,
|
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata,
|
//
|
|
// These wires allow us to push how we deal with the RAM
|
|
// to the next level up, where they'll be use to interact
|
|
// with a Xilinx specific core.
|
|
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata, o_ram_sel,
|
i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,
|
i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err,
|
i_ram_dbg,
|
i_ram_dbg,
|
// The SD Card
|
// The SD Card
|
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
|
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
|
// Ethernet control (packets) lines
|
// Ethernet control (packets) lines
|
| Line 137... |
Line 144... |
o_mdclk, o_mdio, o_mdwe, i_mdio,
|
o_mdclk, o_mdio, o_mdwe, i_mdio,
|
// OLED Control interface (roughly SPI)
|
// OLED Control interface (roughly SPI)
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
o_oled_reset_n, o_oled_vccen, o_oled_pmoden,
|
// The GPS PMod
|
// The GPS PMod
|
i_gps_pps, i_gps_3df
|
i_gps_pps, i_gps_3df,
|
|
// Other GPIO wires
|
|
i_gpio, o_gpio
|
);
|
);
|
parameter ZA=28, ZIPINTS=15, RESET_ADDRESS=28'h04e0000;
|
parameter ZA=28, ZIPINTS=14, RESET_ADDRESS=32'h01380000,
|
|
NGPI = 4, NGPO = 1;
|
input i_clk, i_rst;
|
input i_clk, i_rst;
|
// The bus commander, via an external uart port
|
// The bus commander, via an external uart port
|
input i_rx_stb;
|
input i_rx_stb;
|
input [7:0] i_rx_data;
|
input [7:0] i_rx_data;
|
output wire o_tx_stb;
|
output wire o_tx_stb;
|
| Line 153... |
Line 163... |
input [3:0] i_sw; // 16 switch bus
|
input [3:0] i_sw; // 16 switch bus
|
input [3:0] i_btn; // 5 Buttons
|
input [3:0] i_btn; // 5 Buttons
|
output wire [3:0] o_led; // 16 wide LED's
|
output wire [3:0] o_led; // 16 wide LED's
|
output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
|
output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3;
|
// PMod UARTs
|
// PMod UARTs
|
input i_aux_rx;
|
input i_aux_rx, i_aux_cts_n;
|
output wire o_aux_tx, o_aux_cts;
|
output wire o_aux_tx, o_aux_rts_n;
|
input i_gps_rx;
|
input i_gps_rx;
|
output wire o_gps_tx;
|
output wire o_gps_tx;
|
// Quad-SPI flash control
|
// Quad-SPI flash control
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire o_qspi_cs_n, o_qspi_sck;
|
output wire [3:0] o_qspi_dat;
|
output wire [3:0] o_qspi_dat;
|
| Line 170... |
Line 180... |
// These would be our RAM control lines. However, these are device,
|
// These would be our RAM control lines. However, these are device,
|
// implementation, and architecture dependent, rather than just simply
|
// implementation, and architecture dependent, rather than just simply
|
// logic dependent. Therefore, this interface as it exists cannot
|
// logic dependent. Therefore, this interface as it exists cannot
|
// exist here. Instead, we export a device independent wishbone to
|
// exist here. Instead, we export a device independent wishbone to
|
// the RAM rather than the RAM wires themselves.
|
// the RAM rather than the RAM wires themselves.
|
//
|
|
// output wire o_ddr_ck_p, o_ddr_ck_n,o_ddr_reset_n, o_ddr_cke,
|
// output wire o_ddr_ck_p, o_ddr_ck_n,o_ddr_reset_n, o_ddr_cke,
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
// output wire [2:0] o_ddr_ba;
|
// output wire [2:0] o_ddr_ba;
|
// output wire [13:0] o_ddr_addr;
|
// output wire [13:0] o_ddr_addr;
|
// output wire o_ddr_odt;
|
// output wire o_ddr_odt;
|
// output wire [1:0] o_ddr_dm;
|
// output wire [1:0] o_ddr_dm;
|
// inout wire [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
|
// output wire [1:0] o_ddr_dqs;
|
// inout wire [15:0] io_ddr_data;
|
// input wire [15:0] i_ddr_data;
|
|
// output wire [15:0] o_ddr_data;
|
//
|
//
|
output wire o_ram_cyc, o_ram_stb, o_ram_we;
|
output wire o_ram_cyc, o_ram_stb, o_ram_we;
|
output wire [25:0] o_ram_addr;
|
output wire [25:0] o_ram_addr;
|
output wire [31:0] o_ram_wdata;
|
output wire [31:0] o_ram_wdata;
|
|
output wire [3:0] o_ram_sel;
|
input i_ram_ack, i_ram_stall;
|
input i_ram_ack, i_ram_stall;
|
input [31:0] i_ram_rdata;
|
input [31:0] i_ram_rdata;
|
input i_ram_err;
|
input i_ram_err;
|
input [31:0] i_ram_dbg;
|
input [31:0] i_ram_dbg;
|
// The SD Card
|
// The SD Card
|
| Line 212... |
Line 224... |
o_oled_dcn, o_oled_reset_n, o_oled_vccen,
|
o_oled_dcn, o_oled_reset_n, o_oled_vccen,
|
o_oled_pmoden;
|
o_oled_pmoden;
|
// GPS PMod (GPS UART above)
|
// GPS PMod (GPS UART above)
|
input i_gps_pps;
|
input i_gps_pps;
|
input i_gps_3df;
|
input i_gps_3df;
|
|
// Other GPIO wires
|
|
input [(NGPI-1):0] i_gpio;
|
|
output wire [(NGPO-1):0] o_gpio;
|
|
|
//
|
//
|
//
|
//
|
// Master wishbone wires
|
// Master wishbone wires
|
//
|
//
|
//
|
//
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_err, ram_err;
|
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_err, ram_err;
|
wire [31:0] wb_data, wb_addr;
|
wire [31:0] wb_data;
|
|
wire [(ZA-1):0] wb_addr;
|
|
wire [3:0] wb_sel;
|
reg wb_ack;
|
reg wb_ack;
|
reg [31:0] wb_idata;
|
reg [31:0] wb_idata;
|
|
|
// Interrupts
|
// Interrupts
|
wire gpio_int, oled_int, flash_int, scop_int;
|
wire gpio_int, oled_int, flash_int, scop_int;
|
wire enet_tx_int, enet_rx_int, sdcard_int, rtc_int, rtc_pps,
|
wire enet_tx_int, enet_rx_int, sdcard_int, rtc_int, rtc_pps,
|
|
auxrxf_int, auxtxf_int, gpsrxf_int, gpstxf_int,
|
auxrx_int, auxtx_int, gpsrx_int, gpstx_int,
|
auxrx_int, auxtx_int, gpsrx_int, gpstx_int,
|
sw_int, btn_int;
|
sw_int, btn_int;
|
|
|
//
|
//
|
//
|
//
|
| Line 239... |
Line 257... |
wire [31:0] dwb_idata;
|
wire [31:0] dwb_idata;
|
|
|
// Wires going to devices
|
// Wires going to devices
|
wire wbu_cyc, wbu_stb, wbu_we;
|
wire wbu_cyc, wbu_stb, wbu_we;
|
wire [31:0] wbu_addr, wbu_data;
|
wire [31:0] wbu_addr, wbu_data;
|
|
wire [3:0] wbu_sel;
|
// and then coming from devices
|
// and then coming from devices
|
wire wbu_ack, wbu_stall, wbu_err;
|
wire wbu_ack, wbu_stall, wbu_err;
|
wire [31:0] wbu_idata;
|
wire [31:0] wbu_idata;
|
// And then headed back home
|
// And then headed back home
|
wire w_interrupt;
|
wire w_bus_interrupt;
|
// Oh, and the debug control for the ZIP CPU
|
// Oh, and the debug control for the ZIP CPU
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
|
wire [31:0] zip_dbg_data;
|
wire [31:0] zip_dbg_data;
|
`ifdef WBU_SCOPE
|
`ifdef WBU_SCOPE
|
wire [31:0] wbu_debug;
|
wire [31:0] wbu_debug;
|
| Line 256... |
Line 275... |
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
|
(wbu_zip_sel)?zip_dbg_ack:wbu_ack,
|
(wbu_zip_sel)?zip_dbg_ack:wbu_ack,
|
(wbu_zip_sel)?zip_dbg_stall:wbu_stall,
|
(wbu_zip_sel)?zip_dbg_stall:wbu_stall,
|
wbu_err,
|
wbu_err,
|
(wbu_zip_sel)?zip_dbg_data:wbu_idata,
|
(wbu_zip_sel)?zip_dbg_data:wbu_idata,
|
w_interrupt,
|
w_bus_interrupt,
|
o_tx_stb, o_tx_data, i_tx_busy
|
o_tx_stb, o_tx_data, i_tx_busy
|
// , wbu_debug
|
// , wbu_debug
|
);
|
);
|
|
assign wbu_sel = 4'hf;
|
|
|
`ifdef WBU_SCOPE
|
`ifdef WBU_SCOPE
|
// assign o_dbg = (wbu_ack)&&(wbu_cyc);
|
// assign o_dbg = (wbu_ack)&&(wbu_cyc);
|
assign wbu_debug = { wbu_cyc, wbu_stb, wbu_we, wbu_ack, wbu_stall,
|
assign wbu_debug = { wbu_cyc, wbu_stb, wbu_we, wbu_ack, wbu_stall,
|
wbu_err, wbu_zip_sel,
|
wbu_err, wbu_zip_sel,
|
| Line 283... |
Line 303... |
//
|
//
|
// Second BUS master source: The ZipCPU
|
// Second BUS master source: The ZipCPU
|
//
|
//
|
//
|
//
|
wire zip_cyc, zip_stb, zip_we;
|
wire zip_cyc, zip_stb, zip_we;
|
wire [(ZA-1):0] w_zip_addr;
|
wire [(ZA-1):0] zip_addr;
|
wire [31:0] zip_data, zip_scope_data;
|
wire [31:0] zip_data, zip_scope_data;
|
|
wire [3:0] zip_sel;
|
// and then coming from devices
|
// and then coming from devices
|
wire zip_ack, zip_stall, zip_err;
|
wire zip_ack, zip_stall, zip_err;
|
|
|
`ifdef ZIP_SYSTEM
|
`ifdef ZIP_SYSTEM
|
wire [(ZIPINTS-1):0] zip_interrupt_vec = {
|
wire [(ZIPINTS-1):0] zip_interrupt_vec = {
|
// Lazy(ier) interrupts
|
// Lazy(ier) interrupts
|
gpio_int, scop_int, flash_int, sw_int, btn_int, rtc_int,
|
|
// Fast interrupts
|
|
oled_int, sdcard_int,
|
|
gpstx_int, gpsrx_int,
|
gpstx_int, gpsrx_int,
|
auxtx_int, auxrx_int,
|
auxtx_int, auxrx_int,
|
|
rtc_ppd,
|
|
// Fast interrupts
|
|
oled_int, w_bus_interrupt,
|
|
gpstxf_int, gpsrxf_int,
|
|
auxtxf_int, auxrxf_int,
|
enet_tx_int, enet_rx_int, rtc_pps
|
enet_tx_int, enet_rx_int, rtc_pps
|
};
|
};
|
|
|
zipsystem #( .RESET_ADDRESS(RESET_ADDRESS),
|
zipsystem #( .RESET_ADDRESS(RESET_ADDRESS),
|
.ADDRESS_WIDTH(ZA),
|
.ADDRESS_WIDTH(ZA),
|
.LGICACHE(10),
|
.LGICACHE(10),
|
.START_HALTED(1),
|
.START_HALTED(1),
|
.EXTERNAL_INTERRUPTS(ZIPINTS),
|
.EXTERNAL_INTERRUPTS(ZIPINTS))
|
.HIGHSPEED_CPU(0))
|
swic(i_clk, i_rst,
|
zippy(i_clk, i_rst,
|
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_interrupt_vec, zip_cpu_int,
|
zip_interrupt_vec, zip_cpu_int,
|
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
| Line 324... |
Line 346... |
`else // ZIP_SYSTEM
|
`else // ZIP_SYSTEM
|
wire w_zip_cpu_int_ignored;
|
wire w_zip_cpu_int_ignored;
|
zipbones #( .RESET_ADDRESS(RESET_ADDRESS),
|
zipbones #( .RESET_ADDRESS(RESET_ADDRESS),
|
.ADDRESS_WIDTH(ZA),
|
.ADDRESS_WIDTH(ZA),
|
.LGICACHE(10),
|
.LGICACHE(10),
|
.START_HALTED(1),
|
.START_HALTED(1))
|
.HIGHSPEED_CPU(0))
|
swic(i_clk, i_rst,
|
zippy(i_clk, i_rst,
|
|
// Zippys wishbone interface
|
// Zippys wishbone interface
|
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
zip_ack, zip_stall, dwb_idata, zip_err,
|
w_interrupt, w_zip_cpu_int_ignored,
|
w_bus_interrupt, w_zip_cpu_int_ignored,
|
// Debug wishbone interface
|
// Debug wishbone interface
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_cyc)&&(wbu_zip_sel)),
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0],
|
wbu_data,
|
wbu_data,
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
zip_dbg_ack, zip_dbg_stall, zip_dbg_data
|
| Line 343... |
Line 364... |
`endif
|
`endif
|
);
|
);
|
assign zip_cpu_int = 1'b0;
|
assign zip_cpu_int = 1'b0;
|
`endif // ZIP_SYSTEM v ZIP_BONES
|
`endif // ZIP_SYSTEM v ZIP_BONES
|
|
|
wire [31:0] zip_addr;
|
|
generate
|
|
if (ZA < 32)
|
|
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr};
|
|
else
|
|
assign zip_addr = w_zip_addr;
|
|
endgenerate
|
|
|
|
//
|
//
|
//
|
//
|
// And an arbiter to decide who gets to access the bus
|
// And an arbiter to decide who gets to access the bus
|
//
|
//
|
//
|
//
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
|
wire [31:0] dwb_addr, dwb_odata;
|
wire [(ZA-1):0] dwb_addr;
|
wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk,
|
wire [31:0] dwb_odata;
|
|
wire [3:0] dwb_sel;
|
|
wbpriarbiter #(32,ZA) wbu_zip_arbiter(i_clk,
|
// The ZIP CPU Master -- Gets the priority slot
|
// The ZIP CPU Master -- Gets the priority slot
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data,
|
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel,
|
zip_ack, zip_stall, zip_err,
|
zip_ack, zip_stall, zip_err,
|
// The UART interface Master
|
// The UART interface Master
|
(wbu_cyc)&&(!wbu_zip_sel), (wbu_stb)&&(!wbu_zip_sel), wbu_we,
|
(wbu_cyc)&&(!wbu_zip_sel), (wbu_stb)&&(!wbu_zip_sel), wbu_we,
|
wbu_addr, wbu_data,
|
wbu_addr[(ZA-1):0], wbu_data, wbu_sel,
|
wbu_ack, wbu_stall, wbu_err,
|
wbu_ack, wbu_stall, wbu_err,
|
// Common bus returns
|
// Common bus returns
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel,
|
dwb_ack, dwb_stall, dwb_err);
|
dwb_ack, dwb_stall, dwb_err);
|
|
|
//
|
//
|
//
|
//
|
// And because the ZIP CPU and the Arbiter create an unacceptable
|
// And because the ZIP CPU and the Arbiter create an unacceptable
|
// delay, we fail timing. So we add in a delay cycle ...
|
// delay, we fail timing. So we add in a delay cycle ...
|
//
|
//
|
//
|
//
|
assign wbu_idata = dwb_idata;
|
assign wbu_idata = dwb_idata;
|
busdelay wbu_zip_delay(i_clk,
|
busdelay #(ZA) wbu_zip_delay(i_clk,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata,
|
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel,
|
dwb_ack, dwb_stall, dwb_idata, dwb_err,
|
dwb_ack, dwb_stall, dwb_idata, dwb_err,
|
wb_cyc, wb_stb, wb_we, wb_addr, wb_data,
|
wb_cyc, wb_stb, wb_we, wb_addr, wb_data, wb_sel,
|
wb_ack, wb_stall, wb_idata, wb_err);
|
wb_ack, wb_stall, wb_idata, wb_err);
|
|
|
`else // ZIPCPU
|
`else // ZIPCPU
|
assign zip_cpu_int = 1'b0; // No CPU here to halt
|
assign zip_cpu_int = 1'b0; // No CPU here to halt
|
assign wbu_zip_sel = 1'b0;
|
assign wbu_zip_sel = 1'b0;
|
| Line 395... |
Line 410... |
assign wb_cyc = wbu_cyc;
|
assign wb_cyc = wbu_cyc;
|
assign wb_stb = wbu_stb;
|
assign wb_stb = wbu_stb;
|
assign wb_we = wbu_we;
|
assign wb_we = wbu_we;
|
assign wb_addr = wbu_addr;
|
assign wb_addr = wbu_addr;
|
assign wb_data = wbu_data;
|
assign wb_data = wbu_data;
|
|
assign wb_sel = wbu_sel;
|
assign wbu_idata = wb_idata;
|
assign wbu_idata = wb_idata;
|
assign wbu_ack = wb_ack;
|
assign wbu_ack = wb_ack;
|
assign wbu_stall = wb_stall;
|
assign wbu_stall = wb_stall;
|
assign wbu_err = wb_err;
|
assign wbu_err = wb_err;
|
|
|
| Line 415... |
Line 431... |
// line selects the given I/O peripheral. The none_sel and many_sel
|
// line selects the given I/O peripheral. The none_sel and many_sel
|
// lines are used to detect problems, such as when no device is
|
// lines are used to detect problems, such as when no device is
|
// selected or many devices are selected. Such problems will lead to
|
// selected or many devices are selected. Such problems will lead to
|
// bus errors (below).
|
// bus errors (below).
|
//
|
//
|
wire io_sel, scop_sel, netb_sel,
|
wire io_sel, scop_sel, rtc_sel, oled_sel, uart_sel, gpsu_sel,
|
flctl_sel, rtc_sel, sdcard_sel, netp_sel,
|
sdcard_sel, gps_sel, netp_sel, mio_sel, cfg_sel,
|
oled_sel, gps_sel, mio_sel, cfg_sel,
|
ram_sel, flash_sel, flctl_sel, mem_sel, netb_sel,
|
mem_sel, flash_sel, ram_sel,
|
|
none_sel, many_sel;
|
none_sel, many_sel;
|
|
|
|
wire idle_n;
|
|
`ifdef ZERO_ON_IDLE
|
|
assign idle_n = wb_stb;
|
|
`else
|
|
assign idle_n = 1'b1;
|
|
`endif
|
wire [4:0] skipaddr;
|
wire [4:0] skipaddr;
|
assign skipaddr = { wb_addr[26], wb_addr[22], wb_addr[15], wb_addr[11],
|
assign skipaddr = { wb_addr[26], wb_addr[22], wb_addr[15], wb_addr[11],
|
~wb_addr[8] };
|
~wb_addr[8] };
|
assign ram_sel = (skipaddr[4]);
|
assign ram_sel = (idle_n)&&(skipaddr[4]);
|
assign flash_sel = (skipaddr[4:3]==2'b01);
|
assign flash_sel = (idle_n)&&(skipaddr[4:3]==2'b01);
|
assign mem_sel = (skipaddr[4:2]==3'b001);
|
assign mem_sel = (idle_n)&&(skipaddr[4:2]==3'b001);
|
assign netb_sel = (skipaddr[4:1]==4'b0001);
|
assign netb_sel = (idle_n)&&(skipaddr[4:1]==4'b0001);
|
assign io_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b000);
|
assign io_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b00_0);
|
assign scop_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0010_0);
|
assign scop_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b00_100);
|
assign rtc_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0010_10);
|
assign rtc_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1010);
|
assign sdcard_sel= (~|skipaddr)&&(wb_addr[7:2]==6'b0010_11);
|
assign oled_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1011);
|
//assign gps_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_00);
|
assign uart_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1100);
|
assign oled_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_01);
|
assign gpsu_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1101);
|
assign netp_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0011_1);
|
assign sdcard_sel= (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1110);
|
assign gps_sel = (~|skipaddr)&&( (wb_addr[7:2]==6'b0011_00)
|
//assign unused_ = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1111);
|
|| (wb_addr[7:3]==5'b0100_0));
|
assign gps_sel = (idle_n)&&(~|skipaddr)&&((wb_addr[7:2]==6'b01_0000)
|
assign mio_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b101);
|
||(wb_addr[7:3]==5'b01_001));
|
assign flctl_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b110);
|
assign netp_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b01_010);
|
assign cfg_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b111);
|
assign mio_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b01_1);
|
|
assign flctl_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_0);
|
|
assign cfg_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_1);
|
|
|
wire skiperr;
|
wire skiperr;
|
assign skiperr = (|wb_addr[31:27])
|
assign skiperr = (idle_n)&&((|wb_addr[(ZA-1):27])
|
||(~skipaddr[4])&&(|wb_addr[25:23])
|
||(~skipaddr[4])&&(|wb_addr[25:23])
|
||(skipaddr[4:3]==2'b00)&&(|wb_addr[21:16])
|
||(skipaddr[4:3]==2'b00)&&(|wb_addr[21:16])
|
||(skipaddr[4:2]==3'b000)&&(|wb_addr[14:12])
|
||(skipaddr[4:2]==3'b000)&&(|wb_addr[14:12])
|
||(skipaddr[4:1]==4'b0000)&&(|wb_addr[10:9]);
|
||(skipaddr[4:1]==4'b0000)&&(|wb_addr[10:9])
|
|
||(skipaddr[4:0]==5'b00001));
|
|
|
|
|
//
|
//
|
// Peripheral acknowledgement lines
|
// Peripheral acknowledgement lines
|
//
|
//
|
// These are only a touch more confusing, since the flash device will
|
// These are only a touch more confusing, since the flash device will
|
// ACK for both flctl_sel (the control line select), as well as the
|
// ACK for both flctl_sel (the control line select), as well as the
|
// flash_sel (the memory line select). Hence we have one fewer ack
|
// flash_sel (the memory line select). Hence we have one fewer ack
|
// line.
|
// line.
|
wire io_ack, oled_ack,
|
wire io_ack, rtc_ack, oled_ack, uart_ack, gpsu_ack, sdcard_ack,
|
rtc_ack, sdcard_ack,
|
gps_ack, net_ack, mio_ack, cfg_ack,
|
net_ack, gps_ack, mio_ack, cfg_ack,
|
|
mem_ack, flash_ack, ram_ack;
|
mem_ack, flash_ack, ram_ack;
|
|
|
reg many_ack, slow_many_ack;
|
reg many_ack, slow_many_ack;
|
reg slow_ack, scop_ack;
|
reg slow_ack, scop_ack;
|
wire [4:0] ack_list;
|
wire [4:0] ack_list;
|
assign ack_list = { ram_ack, flash_ack, mem_ack, net_ack, slow_ack };
|
assign ack_list = { ram_ack, flash_ack, mem_ack, net_ack, slow_ack };
|
initial many_ack = 1'b0;
|
initial many_ack = 1'b0;
|
| Line 472... |
Line 496... |
&&(ack_list != 5'h8)
|
&&(ack_list != 5'h8)
|
&&(ack_list != 5'h4)
|
&&(ack_list != 5'h4)
|
&&(ack_list != 5'h2)
|
&&(ack_list != 5'h2)
|
&&(ack_list != 5'h1)
|
&&(ack_list != 5'h1)
|
&&(ack_list != 5'h0));
|
&&(ack_list != 5'h0));
|
/*
|
wire [9:0] slow_ack_list;
|
assign many_ack = ( { 2'h0, ram_ack}
|
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack, uart_ack, gpsu_ack,
|
+{2'h0, flash_ack }
|
|
+{2'h0, mem_ack }
|
|
+{2'h0, slow_ack } > 3'h1 );
|
|
*/
|
|
|
|
wire [7:0] slow_ack_list;
|
|
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack,
|
|
sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
|
sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack };
|
initial slow_many_ack = 1'b0;
|
initial slow_many_ack = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
slow_many_ack <= ((slow_ack_list != 8'h80)
|
slow_many_ack <= ((slow_ack_list != 10'h200)
|
&&(slow_ack_list != 8'h40)
|
&&(slow_ack_list != 10'h100)
|
&&(slow_ack_list != 8'h20)
|
&&(slow_ack_list != 10'h080)
|
&&(slow_ack_list != 8'h10)
|
&&(slow_ack_list != 10'h040)
|
&&(slow_ack_list != 8'h08)
|
&&(slow_ack_list != 10'h020)
|
&&(slow_ack_list != 8'h04)
|
&&(slow_ack_list != 10'h010)
|
&&(slow_ack_list != 8'h02)
|
&&(slow_ack_list != 10'h008)
|
&&(slow_ack_list != 8'h01)
|
&&(slow_ack_list != 10'h004)
|
&&(slow_ack_list != 8'h00));
|
&&(slow_ack_list != 10'h002)
|
|
&&(slow_ack_list != 10'h001)
|
|
&&(slow_ack_list != 10'h000));
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
wb_ack <= (wb_cyc)&&(|ack_list);
|
wb_ack <= (wb_cyc)&&(|ack_list);
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
slow_ack <= (wb_cyc)&&(|slow_ack_list);
|
slow_ack <= (wb_cyc)&&(|slow_ack_list);
|
|
|
//
|
//
|
// Peripheral data lines
|
// Peripheral data lines
|
//
|
//
|
wire [31:0] io_data, oled_data,
|
wire [31:0] io_data, rtc_data, oled_data, uart_data, gpsu_data,
|
rtc_data, sdcard_data,
|
sdcard_data,
|
net_data, gps_data, mio_data, cfg_data,
|
net_data, gps_data, mio_data, cfg_data,
|
mem_data, flash_data, ram_data;
|
mem_data, flash_data, ram_data;
|
reg [31:0] slow_data, scop_data;
|
reg [31:0] slow_data, scop_data;
|
|
|
// 4 control lines, 5x32 data lines ...
|
// 4 control lines, 5x32 data lines ...
|
| Line 517... |
Line 536... |
else if ((mem_ack)||(net_ack))
|
else if ((mem_ack)||(net_ack))
|
wb_idata <= (mem_ack)?mem_data:net_data;
|
wb_idata <= (mem_ack)?mem_data:net_data;
|
else
|
else
|
wb_idata <= slow_data;
|
wb_idata <= slow_data;
|
|
|
// 7 control lines, 8x32 data lines
|
// 9 control lines, 10x32 data lines
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((cfg_ack)||(mio_ack))
|
if ((cfg_ack)||(mio_ack))
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
slow_data <= (cfg_ack) ? cfg_data : mio_data;
|
|
else if ((uart_ack)||(gpsu_ack))
|
|
slow_data <= (uart_ack)?uart_data : gpsu_data;
|
else if ((sdcard_ack)||(rtc_ack))
|
else if ((sdcard_ack)||(rtc_ack))
|
slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
|
slow_data <= (sdcard_ack)?sdcard_data : rtc_data;
|
else if ((scop_ack)|(oled_ack))
|
else if ((scop_ack)|(oled_ack))
|
slow_data <= (scop_ack)?scop_data:oled_data;
|
slow_data <= (scop_ack)?scop_data:oled_data;
|
else
|
else
|
| Line 535... |
Line 556... |
//
|
//
|
// As per the wishbone spec, these cannot be clocked or delayed. They
|
// As per the wishbone spec, these cannot be clocked or delayed. They
|
// *must* be done via combinatorial logic.
|
// *must* be done via combinatorial logic.
|
//
|
//
|
wire io_stall, scop_stall, oled_stall,
|
wire io_stall, scop_stall, oled_stall,
|
rtc_stall, sdcard_stall,
|
rtc_stall, sdcard_stall, uart_stall, gpsu_stall,
|
net_stall, gps_stall, mio_stall, cfg_stall, netb_stall,
|
net_stall, gps_stall, mio_stall, cfg_stall, netb_stall,
|
mem_stall, flash_stall, ram_stall,
|
mem_stall, flash_stall, ram_stall,
|
many_stall;
|
many_stall;
|
assign wb_stall = (wb_cyc)&&(
|
assign wb_stall = (wb_cyc)&&(
|
((io_sel)&&(io_stall)) // Never stalls
|
((io_sel)&&(io_stall)) // Never stalls
|
||((scop_sel)&&(scop_stall)) // Never stalls
|
||((scop_sel)&&(scop_stall)) // Never stalls
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
||((rtc_sel)&&(rtc_stall)) // Never stalls
|
|
||((oled_sel)&&(oled_stall)) // Never stalls
|
|
||((uart_sel)&&(uart_stall)) // Never stalls
|
|
||((gpsu_sel)&&(gpsu_stall)) // Never stalls
|
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
||((sdcard_sel)&&(sdcard_stall))// Never stalls
|
||((netp_sel)&&(net_stall)) // Never stalls
|
||((netp_sel)&&(net_stall)) // Never stalls
|
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?)
|
||((oled_sel)&&(oled_stall)) // Never stalls
|
|
||((mio_sel)&&(mio_stall))
|
||((mio_sel)&&(mio_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((cfg_sel)&&(cfg_stall))
|
||((netb_sel)&&(net_stall)) // Never stalls
|
||((netb_sel)&&(net_stall)) // Never stalls
|
||((mem_sel)&&(mem_stall)) // Never stalls
|
||((mem_sel)&&(mem_stall)) // Never stalls
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
||((flash_sel|flctl_sel)&&(flash_stall))
|
| Line 574... |
Line 597... |
// Selecting multiple devices at once is a design flaw that should
|
// Selecting multiple devices at once is a design flaw that should
|
// never happen. Hence, if this logic won't build, we won't include
|
// never happen. Hence, if this logic won't build, we won't include
|
// it. Still, having this logic in place has saved my tush more than
|
// it. Still, having this logic in place has saved my tush more than
|
// once.
|
// once.
|
//
|
//
|
reg [31:0] sel_addr;
|
reg [(ZA-1):0] sel_addr;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
sel_addr <= wb_addr;
|
sel_addr <= wb_addr;
|
|
|
reg many_sel_a, many_sel_b, single_sel_a, single_sel_b, last_stb;
|
reg many_sel_a, many_sel_b, single_sel_a, single_sel_b, last_stb;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
last_stb <= wb_stb;
|
last_stb <= wb_stb;
|
|
|
single_sel_a <= (wb_stb)&&((ram_sel)|(flash_sel)
|
single_sel_a <= (wb_stb)&&((ram_sel)|(flash_sel)
|
|(mem_sel)|(netb_sel)|(cfg_sel));
|
|(mem_sel)|(netb_sel)|(cfg_sel)
|
|
|(uart_sel)|(gpsu_sel));
|
many_sel_a <= 1'b0;
|
many_sel_a <= 1'b0;
|
if ((ram_sel)&&((flash_sel)||(mem_sel)||(netb_sel)||cfg_sel))
|
if ((ram_sel)&&((flash_sel)||(mem_sel)||(netb_sel)||(cfg_sel)
|
|
||(uart_sel)||(gpsu_sel)))
|
|
many_sel_a <= 1'b1;
|
|
else if ((flash_sel)&&((mem_sel)||(netb_sel)||(cfg_sel)
|
|
||(uart_sel)||(gpsu_sel)))
|
|
many_sel_a <= 1'b1;
|
|
else if ((mem_sel)&&((netb_sel)||(cfg_sel)
|
|
||(uart_sel)||(gpsu_sel)))
|
many_sel_a <= 1'b1;
|
many_sel_a <= 1'b1;
|
else if ((flash_sel)&&((mem_sel)||(netb_sel)||cfg_sel))
|
else if ((netb_sel)&&((cfg_sel)||(uart_sel)||(gpsu_sel)))
|
many_sel_a <= 1'b1;
|
many_sel_a <= 1'b1;
|
else if ((mem_sel)&&((netb_sel)||cfg_sel))
|
else if ((cfg_sel)&&((uart_sel)||(gpsu_sel)))
|
many_sel_a <= 1'b1;
|
many_sel_a <= 1'b1;
|
else if ((netb_sel)&&(cfg_sel))
|
else if ((uart_sel)&&(gpsu_sel))
|
many_sel_a <= 1'b1;
|
many_sel_a <= 1'b1;
|
|
|
single_sel_b <= (wb_stb)&&((mio_sel)||(gps_sel)||(netp_sel)
|
single_sel_b <= (wb_stb)&&((mio_sel)||(gps_sel)||(netp_sel)
|
||(sdcard_sel)||(rtc_sel)||(flctl_sel)
|
||(sdcard_sel)||(rtc_sel)||(flctl_sel)
|
||(oled_sel)||(scop_sel)||(io_sel));
|
||(oled_sel)||(scop_sel)||(io_sel));
|
| Line 622... |
Line 653... |
else if ((oled_sel)&&(io_sel))
|
else if ((oled_sel)&&(io_sel))
|
many_sel_b <= 1'b1;
|
many_sel_b <= 1'b1;
|
end
|
end
|
|
|
wire sel_err; // 5 inputs
|
wire sel_err; // 5 inputs
|
assign sel_err = ( (last_stb)&&(~single_sel_a)&&(~single_sel_b))
|
assign sel_err = ( (last_stb)&&(!single_sel_a)&&(!single_sel_b))
|
||((single_sel_a)&&(single_sel_b))
|
||((single_sel_a)&&(single_sel_b))
|
||((single_sel_a)&&(many_sel_a))
|
||((single_sel_a)&&(many_sel_a))
|
||((single_sel_b)&&(many_sel_b));
|
||((single_sel_b)&&(many_sel_b));
|
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack||ram_err);
|
assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack||ram_err);
|
|
|
| Line 635... |
Line 666... |
// the error will be important to figuring out how to fix it. Hence,
|
// the error will be important to figuring out how to fix it. Hence,
|
// we grab it here. Be aware, however, that this might not truly be
|
// we grab it here. Be aware, however, that this might not truly be
|
// the address that caused an error: in the case of none_sel it will
|
// the address that caused an error: in the case of none_sel it will
|
// be, but if many_ack or slow_many_ack are true then we might just be
|
// be, but if many_ack or slow_many_ack are true then we might just be
|
// looking at an address on the bus that was nearby the one requested.
|
// looking at an address on the bus that was nearby the one requested.
|
reg [31:0] bus_err_addr;
|
reg [(ZA-1):0] r_bus_err_addr;
|
initial bus_err_addr = 32'h00;
|
initial r_bus_err_addr = 0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (wb_err)
|
if (wb_err)
|
bus_err_addr <= sel_addr;
|
r_bus_err_addr <= sel_addr;
|
|
wire [31:0] bus_err_addr;
|
|
assign bus_err_addr[(ZA+1):0] = { r_bus_err_addr, 2'b00 };
|
|
generate if (ZA < 30)
|
|
assign bus_err_addr[31:(ZA+2)] = 0;
|
|
endgenerate
|
|
|
//
|
//
|
// I/O peripheral
|
// I/O peripheral
|
//
|
//
|
// The I/O processor, herein called an fastio. This is a unique
|
// The I/O processor, herein called an fastio. This is a unique
|
| Line 652... |
Line 688... |
// answer the bus before their clock. Hence, the fastio simply consists
|
// answer the bus before their clock. Hence, the fastio simply consists
|
// of a mux that selects between various peripheral responses. Further,
|
// of a mux that selects between various peripheral responses. Further,
|
// these peripherals are not allowed to stall the bus.
|
// these peripherals are not allowed to stall the bus.
|
//
|
//
|
// There is no option for turning these off--they will always be on.
|
// There is no option for turning these off--they will always be on.
|
wire [8:0] master_ints;
|
wire [11:0] master_ints;
|
assign master_ints = { zip_cpu_int, oled_int, rtc_int, sdcard_int,
|
assign master_ints = { zip_cpu_int,
|
|
gpsrx_int, auxtx_int, auxrx_int,
|
|
oled_int, rtc_int, sdcard_int,
|
enet_tx_int, enet_rx_int,
|
enet_tx_int, enet_rx_int,
|
scop_int, flash_int, rtc_pps };
|
scop_int, flash_int, rtc_pps };
|
wire [6:0] board_ints;
|
wire [2:0] board_ints;
|
wire [3:0] w_led;
|
wire [3:0] w_led;
|
wire rtc_ppd;
|
wire rtc_ppd;
|
fastio #(
|
fastio #(
|
.AUXUART_SETUP(30'd705), // 115200 Baud, 8N1, from 81.25M
|
.EXTRACLOCK(0), .NGPI(NGPI), .NGPO(NGPO)
|
.GPSUART_SETUP(30'd8464), // 9600 Baud, 8N1
|
|
.EXTRACLOCK(0)
|
|
) runio(i_clk, i_sw, i_btn,
|
) runio(i_clk, i_sw, i_btn,
|
w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3,
|
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx,
|
i_gpio, o_gpio,
|
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0],
|
wb_data, io_ack, io_stall, io_data,
|
wb_data, io_ack, io_stall, io_data,
|
rtc_ppd,
|
rtc_ppd,
|
bus_err_addr, gps_now[63:32], gps_step[47:16],
|
bus_err_addr, gps_now[63:32], gps_step[47:16],
|
master_ints, w_interrupt,
|
master_ints, w_bus_interrupt,
|
board_ints);
|
board_ints);
|
assign { gpio_int, auxrx_int, auxtx_int, gpsrx_int, gpstx_int, sw_int, btn_int } = board_ints;
|
assign { gpio_int, sw_int, btn_int } = board_ints;
|
|
|
/*
|
|
reg [25:0] dbg_counter_err, dbg_counter_cyc, dbg_counter_sel,
|
|
dbg_counter_many;
|
|
// assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack);
|
|
always @(posedge i_clk)
|
|
if (wbu_cyc)
|
|
dbg_counter_cyc <= 0;
|
|
else if (!dbg_counter_cyc[25])
|
|
dbg_counter_cyc <= dbg_counter_cyc+26'h1;
|
|
always @(posedge i_clk)
|
|
if (wbu_err)
|
|
dbg_counter_err <= 0;
|
|
else if (!dbg_counter_err[25])
|
|
dbg_counter_err <= dbg_counter_err+26'h1;
|
|
always @(posedge i_clk)
|
|
if ((wb_cyc)&&(sel_err))
|
|
dbg_counter_sel <= 0;
|
|
else if (!dbg_counter_sel[25])
|
|
dbg_counter_sel <= dbg_counter_sel+26'h1;
|
|
always @(posedge i_clk)
|
|
if ((wb_cyc)&&(many_ack))
|
|
dbg_counter_many <= 0;
|
|
else if (!dbg_counter_many[25])
|
|
dbg_counter_many <= dbg_counter_many+26'h1;
|
|
assign o_led = {
|
|
(!dbg_counter_many[25])|w_led[3],
|
|
(!dbg_counter_sel[25])|w_led[2],
|
|
(!dbg_counter_cyc[25])|w_led[1],
|
|
(!dbg_counter_err[25])|w_led[0] };
|
|
*/
|
|
assign o_led = w_led;
|
assign o_led = w_led;
|
|
|
|
|
//
|
//
|
//
|
//
|
| Line 740... |
Line 746... |
assign rtc_ack = r_rtc_ack;
|
assign rtc_ack = r_rtc_ack;
|
assign rtc_stall = 1'b0;
|
assign rtc_stall = 1'b0;
|
|
|
//
|
//
|
//
|
//
|
|
// Auxilliary UART (console port)
|
|
//
|
|
//
|
|
wbuart #(31'd705) // 115200 Baud, 8N1, from 81.25M
|
|
console(i_clk, 1'b0,
|
|
wb_cyc, (wb_stb)&&(uart_sel), wb_we, wb_addr[1:0], wb_data,
|
|
uart_ack, uart_stall, uart_data,
|
|
i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n,
|
|
auxrx_int, auxtx_int, auxrxf_int, auxtxf_int);
|
|
|
|
//
|
|
//
|
|
// GPS Data UART
|
|
//
|
|
//
|
|
wire gps_rts_n_ignored;
|
|
wbuart #(.INITIAL_SETUP(31'd8464), // 9600 Baud, 8N1
|
|
.HARDWARE_FLOW_CONTROL_PRESENT(1'b0))
|
|
gpsdata(i_clk, 1'b0,
|
|
wb_cyc, (wb_stb)&&(gpsu_sel), wb_we, wb_addr[1:0], wb_data,
|
|
gpsu_ack, gpsu_stall, gpsu_data,
|
|
i_gps_rx, o_gps_tx, 1'b0, gps_rts_n_ignored,
|
|
gpsrx_int, gpstx_int, gpsrxf_int, gpstxf_int);
|
|
|
|
//
|
|
//
|
// SDCard device level access
|
// SDCard device level access
|
//
|
//
|
//
|
//
|
`ifdef SDCARD_ACCESS
|
`ifdef SDCARD_ACCESS
|
wire [31:0] sd_dbg;
|
wire [31:0] sd_dbg;
|
| Line 818... |
Line 850... |
//
|
//
|
wire gps_pps, tb_pps, gps_locked;
|
wire gps_pps, tb_pps, gps_locked;
|
wire [1:0] gps_dbg_tick;
|
wire [1:0] gps_dbg_tick;
|
|
|
gpsclock_tb ppscktb(i_clk, ck_pps, tb_pps,
|
gpsclock_tb ppscktb(i_clk, ck_pps, tb_pps,
|
(wb_stb)&&(gps_sel)&&(!wb_addr[4]),
|
(wb_stb)&&(gps_sel)&&(wb_addr[3]),
|
wb_we, wb_addr[2:0],
|
wb_we, wb_addr[2:0],
|
wb_data, gtb_ack, gtb_stall, gtb_data,
|
wb_data, gtb_ack, gtb_stall, gtb_data,
|
gps_err, gps_now, gps_step);
|
gps_err, gps_now, gps_step);
|
`ifdef GPSTB
|
`ifdef GPSTB
|
assign gps_pps = tb_pps; // Let the truth come from our test bench
|
assign gps_pps = tb_pps; // Let the truth come from our test bench
|
| Line 835... |
Line 867... |
// GPS CLOCK CONTROL
|
// GPS CLOCK CONTROL
|
//
|
//
|
gpsclock #(
|
gpsclock #(
|
.DEFAULT_STEP(32'h834d_c736)
|
.DEFAULT_STEP(32'h834d_c736)
|
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led,
|
(wb_stb)&&(gps_sel)&&(wb_addr[4]),
|
(wb_stb)&&(gps_sel)&&(!wb_addr[3]),
|
wb_we, wb_addr[1:0],
|
wb_we, wb_addr[1:0],
|
wb_data, gck_ack, gck_stall, gck_data,
|
wb_data, gck_ack, gck_stall, gck_data,
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
gps_tracking, gps_now, gps_step, gps_err, gps_locked,
|
gps_dbg_tick);
|
gps_dbg_tick);
|
`else
|
`else
|
| Line 877... |
Line 909... |
wire [31:0] txnet_data;
|
wire [31:0] txnet_data;
|
`endif
|
`endif
|
|
|
enetpackets #(12)
|
enetpackets #(12)
|
netctrl(i_clk, i_rst, wb_cyc,(wb_stb)&&((netp_sel)||(netb_sel)),
|
netctrl(i_clk, i_rst, wb_cyc,(wb_stb)&&((netp_sel)||(netb_sel)),
|
wb_we, { (netb_sel), wb_addr[10:0] }, wb_data,
|
wb_we, { (netb_sel), wb_addr[10:0] }, wb_data, wb_sel,
|
net_ack, net_stall, net_data,
|
net_ack, net_stall, net_data,
|
o_net_reset_n,
|
o_net_reset_n,
|
i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd,
|
i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd,
|
i_net_rxerr,
|
i_net_rxerr,
|
i_net_tx_clk, o_net_tx_en, o_net_txd,
|
i_net_tx_clk, o_net_tx_en, o_net_txd,
|
| Line 908... |
Line 940... |
assign mio_stall = 1'b0;
|
assign mio_stall = 1'b0;
|
assign enet_rx_int = 1'b0;
|
assign enet_rx_int = 1'b0;
|
assign enet_tx_int = 1'b0;
|
assign enet_tx_int = 1'b0;
|
|
|
//
|
//
|
// 2kW memory, 1kW for each of transmit and receive. (Max pkt length
|
// 8kW memory, 4kW for each of transmit and receive. (Max pkt length
|
// is 512W, so this allows for two 512W in memory.) Since we don't
|
// is 512W, so this allows for two 512W in memory.) Since we don't
|
// really have ethernet without ETHERNET_ACCESS defined, this just
|
// really have ethernet without ETHERNET_ACCESS defined, this just
|
// consumes resources for us so we have an idea of what might be
|
// consumes resources for us so we have an idea of what might be
|
// available when we do have ETHERNET_ACCESS defined.
|
// available when we do have ETHERNET_ACCESS defined.
|
//
|
//
|
memdev #(11) enet_buffers(i_clk, wb_cyc, (wb_stb)&&((netb_sel)||(netp_sel)), wb_we,
|
memdev #(13) enet_buffers(i_clk, wb_cyc,
|
wb_addr[10:0], wb_data, net_ack, net_stall, net_data);
|
(wb_stb)&&((netb_sel)||(netp_sel)), wb_we,
|
|
wb_addr[10:0], wb_data, wb_sel, net_ack, net_stall, net_data);
|
assign o_mdclk = 1'b1;
|
assign o_mdclk = 1'b1;
|
assign o_mdio = 1'b1;
|
assign o_mdio = 1'b1;
|
assign o_mdwe = 1'b1;
|
assign o_mdwe = 1'b1;
|
|
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
// MULTIBOOT/ICAPE2 CONFIGURATION ACCESS
|
| Line 946... |
Line 978... |
//
|
//
|
// RAM MEMORY ACCESS
|
// RAM MEMORY ACCESS
|
//
|
//
|
// There is no option to turn this off--this RAM must always be
|
// There is no option to turn this off--this RAM must always be
|
// present in the design.
|
// present in the design.
|
memdev #(.AW(15),
|
memdev #(.LGMEMSZ(17),
|
.EXTRACLOCK(0)) // 32kW, or 128kB, 15 address lines
|
.EXTRACLOCK(0)) // 32kW, or 128kB, 15 address lines
|
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0],
|
wb_data, mem_ack, mem_stall, mem_data);
|
wb_data, wb_sel, mem_ack, mem_stall, mem_data);
|
|
|
//
|
//
|
// FLASH MEMORY ACCESS
|
// FLASH MEMORY ACCESS
|
//
|
//
|
`ifdef FLASH_ACCESS
|
`ifdef FLASH_ACCESS
|
| Line 991... |
Line 1023... |
//
|
//
|
// DDR3-SDRAM
|
// DDR3-SDRAM
|
//
|
//
|
//
|
//
|
`ifdef SDRAM_ACCESS
|
`ifdef SDRAM_ACCESS
|
//wbddrsdram rami(i_clk,
|
/*
|
// wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
wire [31:0] i_ram_dbg;
|
// ram_ack, ram_stall, ram_data,
|
assign i_ram_dbg = 0;
|
// o_ddr_reset_n, o_ddr_cke,
|
wire [1:0] o_ddr_dqs;
|
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
wbddrsdram rami(i_clk,
|
// o_ddr_dqs,
|
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
|
// o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
wb_sel, ram_ack, ram_stall, ram_data,
|
|
o_ddr_reset_n, o_ddr_cke,
|
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
|
o_ddr_dqs,
|
|
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
|
*/
|
assign o_ram_cyc = wb_cyc;
|
assign o_ram_cyc = wb_cyc;
|
assign o_ram_stb = (wb_stb)&&(ram_sel);
|
assign o_ram_stb = (wb_stb)&&(ram_sel);
|
assign o_ram_we = wb_we;
|
assign o_ram_we = wb_we;
|
assign o_ram_addr = wb_addr[25:0];
|
assign o_ram_addr = wb_addr[25:0];
|
assign o_ram_wdata = wb_data;
|
assign o_ram_wdata = wb_data;
|
|
assign o_ram_sel = wb_sel;
|
assign ram_ack = i_ram_ack;
|
assign ram_ack = i_ram_ack;
|
assign ram_stall = i_ram_stall;
|
assign ram_stall = i_ram_stall;
|
assign ram_data = i_ram_rdata;
|
assign ram_data = i_ram_rdata;
|
assign ram_err = i_ram_err;
|
assign ram_err = i_ram_err;
|
/*
|
/*
|
| Line 1036... |
Line 1073... |
|
|
// And idle the DDR3 SDRAM
|
// And idle the DDR3 SDRAM
|
assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset
|
assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset
|
assign o_ddr_cke = 1'b0; // Disable the SDRAM clock
|
assign o_ddr_cke = 1'b0; // Disable the SDRAM clock
|
// DQS
|
// DQS
|
assign o_ddr_dqs = 3'b100; // Leave DQS pins in high impedence
|
assign o_ddr_dqs = 2'b11; // Leave DQS pins in high impedence
|
// DDR3 control wires (not enabled if CKE=0)
|
// DDR3 control wires (not enabled if CKE=0)
|
assign o_ddr_cs_n = 1'b0; // NOOP command
|
assign o_ddr_cs_n = 1'b0; // NOOP command
|
assign o_ddr_ras_n = 1'b1;
|
assign o_ddr_ras_n = 1'b1;
|
assign o_ddr_cas_n = 1'b1;
|
assign o_ddr_cas_n = 1'b1;
|
assign o_ddr_we_n = 1'b1;
|
assign o_ddr_we_n = 1'b1;
|
// (Unused) data wires
|
// (Unused) data wires
|
assign o_ddr_addr = 14'h00;
|
assign o_ddr_addr = 14'h00;
|
assign o_ddr_ba = 3'h0;
|
assign o_ddr_ba = 3'h0;
|
assign o_ddr_data = 32'h00;
|
assign o_ddr_data = 16'h00;
|
`endif
|
`endif
|
|
|
|
|
//
|
//
|
//
|
//
|
| Line 1255... |
Line 1292... |
|
|
assign scop_d_ack = scop_net_ack;
|
assign scop_d_ack = scop_net_ack;
|
assign scop_d_stall = scop_net_stall;
|
assign scop_d_stall = scop_net_stall;
|
assign scop_d_data = scop_net_data;
|
assign scop_d_data = scop_net_data;
|
assign scop_d_interrupt = scop_net_interrupt;
|
assign scop_d_interrupt = scop_net_interrupt;
|
|
|
`else
|
`else
|
assign scop_d_data = 32'h00;
|
assign scop_d_data = 32'h00;
|
assign scop_d_stall = 1'b0;
|
assign scop_d_stall = 1'b0;
|
assign scop_d_interrupt = 1'b0;
|
assign scop_d_interrupt = 1'b0;
|
|
|
